公开(公告)号：US20100290300A1

公开(公告)日：2010-11-18

申请号：US12769141

申请日：2010-04-28

申请人： Hiroyuki TAKAHASHI ,  Tetsuo Fukushi

发明人： Hiroyuki TAKAHASHI ,  Tetsuo Fukushi

IPC分类号： G11C7/00 ,  G11C7/06

CPC分类号： G11C11/4085 ,  G11C7/062 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

摘要： Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage.

摘要翻译： 提供一种包括半导体存储电路和半导体存储电路的外围电路的半导体集成器件。 外围电路包括具有作为栅氧化膜的击穿电压的第一电压的第一晶体管。 半导体存储器电路包括一对位线，一对位线中的一个连接到存储单元的栅极晶体管，以及预充电电路，其包括具有基本上等于第一晶体管的击穿电压的晶体管， 并且响应于激活信号将一对位线预充电到预定电压。 预充电电路的激活信号是比第一电压高的第二电压。

公开(公告)号：US20120262978A1

公开(公告)日：2012-10-18

申请号：US13438731

申请日：2012-04-03

申请人： Hiroyuki TAKAHASHI ,  Seiya YAMANO

发明人： Hiroyuki TAKAHASHI ,  Seiya YAMANO

IPC分类号： G11C5/06 ,  H01L27/088

CPC分类号： H01L29/42376 ,  G11C7/12 ,  G11C7/18 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/10897 ,  H01L29/1095

摘要： Transistors formed in one identical diffusion layer and performing complementary operations are generally arranged symmetrically with respect to the diffusion layer. A semiconductor integrated device using a layout capable of partially avoiding restriction on the design of the semiconductor integrated circuit device and reducing the size and economizing the manufacturing cost is provided by breaking the stereotype idea. The size of the semiconductor integrated circuit device can be decreased further by arranging two transistors formed in one identical diffusion layer and conducting complementary operations by intentionally arranging them in an asymmetric pattern.

摘要翻译： 形成在一个相同扩散层中并执行互补操作的晶体管通常相对于扩散层对称地布置。 使用能够部分地避免对半导体集成电路器件的设计的限制并且减小尺寸并节省制造成本的布局的半导体集成器件通过打破刻板印象的想法来提供。 通过将形成在一个相同的扩散层中的两个晶体管布置并且通过有意地将它们排列成非对称图案来进行互补操作，可以进一步降低半导体集成电路器件的尺寸。

公开(公告)号：US20120226836A1

公开(公告)日：2012-09-06

申请号：US13476619

申请日：2012-05-21

申请人： Hiroyuki TAKAHASHI

发明人： Hiroyuki TAKAHASHI

IPC分类号： G06F13/00

CPC分类号： H03K19/0016 ,  G06F13/4077

摘要： A semiconductor integrated circuit capable of reducing unnecessary current consumption includes a plurality of bus drive circuits for receiving data input, a common bus coupled to the bus drive circuits, and a bus holder coupled to the common bus. One of the bus drive circuits is selected as the selected bus drive circuit. When a logical value corresponding to the data input to be output is the same as a logical value that has been held by the bus holder and output to the common bus, the selected bus drive circuit stops outputting the logical value corresponding to the data input to the common bus. With this configuration, it is possible to eliminate the unnecessary output of the selected bus drive circuit, and to reduce unnecessary current consumption compared to the conventional semiconductor integrated circuit.

摘要翻译： 能够减少不必要的电流消耗的半导体集成电路包括用于接收数据输入的多个总线驱动电路，耦合到总线驱动电路的公共总线和耦合到公共总线的总线保持器。 选择其中一个总线驱动电路作为所选择的总线驱动电路。 当与要输出的数据输入对应的逻辑值与由总线保持器保持并输出到公共总线的逻辑值相同时，所选择的总线驱动电路停止输出与输入的数据相对应的逻辑值 公车。 利用这种配置，可以消除与常规半导体集成电路相比所选择的总线驱动电路的不必要的输出，并且减少不必要的电流消耗。

公开(公告)号：US20090218676A1

公开(公告)日：2009-09-03

申请号：US12393031

申请日：2009-02-25

申请人： Kuniharu MUTO ,  Tadatoshi DANNO ,  Hiroyuki TAKAHASHI

发明人： Kuniharu MUTO ,  Tadatoshi DANNO ,  Hiroyuki TAKAHASHI

IPC分类号： H01L23/48

CPC分类号： H01L24/41 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/84 ,  H01L24/91 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/40091 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48699 ,  H01L2224/48724 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/84205 ,  H01L2224/85207 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/206

摘要： A small-sized surface mount package having a low on-resistance is achieved, in which a power MOSFET etc. is sealed. In one side a molding resin, two silicon chips are sealed. On one side of the molding resin, three source leads and one gate lead are arranged. The three source leads are joined each other inside the molding resin, and the joined portion and a source pad of the silicon chip are electrically coupled each other via two Al ribbons. Moreover, a gate pad of the silicon chip is electrically coupled to the gate lead via one Au wire.

摘要翻译： 实现了具有低导通电阻的小尺寸表面贴装封装，其中功率MOSFET等被密封。 在一方面是模制树脂，两个硅芯片被密封。 在模制树脂的一侧上设置有三个源极引线和一个栅极引线。 三根源极引线在模塑树脂的内部彼此连接，并且硅芯片的接合部分和源极焊盘通过两个Al带彼此电耦合。 此外，硅芯片的栅极焊盘通过一根Au线电连接到栅极引线。

公开(公告)号：US20090109360A1

公开(公告)日：2009-04-30

申请号：US12254853

申请日：2008-10-21

申请人： Hiroyuki TAKAHASHI

发明人： Hiroyuki TAKAHASHI

IPC分类号： G02F1/133

CPC分类号： G02F1/13624 ,  G02F1/134363 ,  G02F1/136213 ,  G09G3/3611 ,  G09G3/3648 ,  G09G3/3659 ,  G09G2300/0426 ,  G09G2300/0809 ,  G09G2300/0861 ,  G09G2310/0254 ,  G09G2310/06

摘要： The present invention provides a liquid crystal display device used in miniaturized portable equipment which exhibits favorable display quality while decreasing a load applied to a driver circuit which supplies a video signal line to pixel electrodes. In a liquid crystal display device which includes liquid crystal display elements and a liquid crystal driving circuit, a boosting circuit is provided to a pixel portion. The boosting circuit, after writing a video signal in a pixel electrode and one electrode of a boosting capacitance, brings the pixel electrode into a floating state. Then, by applying the video signal to another electrode of the boosting capacitance, a voltage of the pixel electrode is boosted or dropped.

摘要翻译： 本发明提供一种在小型便携式设备中使用的液晶显示装置，其显示出良好的显示质量，同时降低施加到向像素电极提供视频信号线的驱动电路的负载。 在包括液晶显示元件和液晶驱动电路的液晶显示装置中，在像素部分设置升压电路。 升压电路在像素电极和升压电容的一个电极中写入视频信号之后，使像素电极成为浮置状态。 然后，通过将视频信号施加到升压电容的另一电极，像素电极的电压被升高或下降。

公开(公告)号：US20090072781A1

公开(公告)日：2009-03-19

申请号：US12206248

申请日：2008-09-08

申请人： Hiroyuki TAKAHASHI ,  Yusuke Ozaki ,  Eiji Nemoto ,  Yuji Matsuda ,  Hiroki Ohkubo

发明人： Hiroyuki TAKAHASHI ,  Yusuke Ozaki ,  Eiji Nemoto ,  Yuji Matsuda ,  Hiroki Ohkubo

IPC分类号： H02J7/35 ,  H02N11/00

CPC分类号： H02J7/35 ,  G03G15/80 ,  Y02E10/566

摘要： A power supply device accumulates charges generated by a photovoltaic unit. The power supply device includes a first capacitor having a first capacitance, in which the charges generated by the photovoltaic unit are charged; a second capacitor having a second capacitance that is larger than the first capacitance; and a switching unit that switches between a first connection of connecting the photovoltaic unit to the first capacitor and a second connection of connecting the first capacitor to the second capacitor.

摘要翻译： 电源装置累积由光电单元产生的电荷。 电源装置包括具有第一电容的第一电容器，其中由光电单元产生的电荷被充电; 具有大于所述第一电容的第二电容的第二电容器; 以及切换单元，其在将光电单元连接到第一电容器的第一连接和将第一电容器连接到第二电容器的第二连接之间切换。

公开(公告)号：US20080191990A1

公开(公告)日：2008-08-14

申请号：US12026613

申请日：2008-02-06

申请人： Hiroyuki MATSUBARA ,  Hiroyuki TAKAHASHI ,  Nobuyuki ORITA ,  Toshiharu OKAMOTO ,  Shuuichi SENOU

发明人： Hiroyuki MATSUBARA ,  Hiroyuki TAKAHASHI ,  Nobuyuki ORITA ,  Toshiharu OKAMOTO ,  Shuuichi SENOU

IPC分类号： G09G3/36

CPC分类号： G09G3/20 ,  G09G3/3685 ,  G09G2310/0275 ,  G09G2330/08

摘要： A driver includes a first memory including a plurality of memory cells and redundant memory cells. An address control circuit replaces a defective memory cell of the plurality of memory cells with one of the redundant memory cells based on a defect address data indicating an address of the defective memory cell. A driving circuit displays on a display panel, a display data stored in the first memory based on a display quality specifying data specifying display quality of the display panel. The display quality specifying data and the defect address data are stored in a second memory.

摘要翻译： 驱动器包括包括多个存储单元和冗余存储单元的第一存储器。 地址控制电路基于指示有缺陷的存储单元的地址的缺陷地址数据，用冗余存储单元之一代替多个存储单元的有缺陷的存储单元。 基于指定显示面板的显示质量的显示质量指定数据，驱动电路在显示面板上显示存储在第一存储器中的显示数据。 显示质量指定数据和缺陷地址数据被存储在第二存储器中。

公开(公告)号：US20080186266A1

公开(公告)日：2008-08-07

申请号：US11971222

申请日：2008-01-09

申请人： Hiroyuki TAKAHASHI

发明人： Hiroyuki TAKAHASHI

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G2330/021 ,  G09G2360/18

摘要： A display driver IC for controlling display of an image on a display panel is provided with a memory and a switch circuit. The memory, in which digital data corresponding to the image is stored, operates with a first voltage. The switch circuit turns ON and OFF supply of the first voltage to the memory. The switch circuit operates with a second voltage that is higher than the first voltage.

摘要翻译： 用于控制显示面板上的图像显示的显示驱动器IC设置有存储器和开关电路。 其中存储对应于图像的数字数据的存储器以第一电压工作。 开关电路将第一电压的ON和OFF供应到存储器。 开关电路以高于第一电压的第二电压工作。

公开(公告)号：US20070167881A1

公开(公告)日：2007-07-19

申请号：US11673392

申请日：2007-02-09

申请人： Hiroyuki TAKAHASHI

发明人： Hiroyuki TAKAHASHI

IPC分类号： A61H1/00

CPC分类号： A61B17/320068

摘要： An ultrasonic operation apparatus comprises a hand piece accommodating an ultrasonic transducer for generating ultrasonic vibrations, a probe which is connected to the hand piece and to which the ultrasonic vibrations are conveyed, a drive signal generating unit for generating a first drive signal that drives the ultrasonic transducer, and a second drive signal the output level of which is different from the first drive signal and for outputting the generated drive signals to the ultrasonic transducer, an output detecting unit for detecting the output current and the output voltage of the second drive signal to the ultrasonic transducer, and a controlling unit, which controls the operations of the drive signal generating unit based on a phase difference between the output voltage and the output current of the second drive signal, for judging the running state of the probe or the hand piece by determining whether or not a resonance frequency at which the phase difference between the output voltage and the output current becomes almost zero can be detected within a predetermined range.

摘要翻译： 一种超声波操作装置，包括容纳用于产生超声波振动的超声波换能器的手柄，连接到手持件并且传送超声波振动的探针，用于产生驱动超声波的第一驱动信号的驱动信号生成单元 换能器和第二驱动信号，其输出电平不同于第一驱动信号，并用于将所产生的驱动信号输出到超声换能器;输出检测单元，用于检测第二驱动信号的输出电流和输出电压， 所述超声波换能器和控制单元，其基于所述第二驱动信号的输出电压和所述输出电流之间的相位差来控制所述驱动信号生成单元的动作，以判断所述探针或所述手持件的行驶状态 通过确定谐振频率是否在相位差之间 可以在预定范围内检测放电电压和输出电流几乎为零。

公开(公告)号：US20110237084A1

公开(公告)日：2011-09-29

申请号：US12729538

申请日：2010-03-23

申请人： Vinh Hoang LUONG ,  Hiroyuki TAKAHASHI ,  Akiteru KO ,  Asao YAMASHITA ,  Vaidyanathan BALASUBRAMANIAM ,  Takashi ENOMOTO ,  Daniel J. PRAGER

发明人： Vinh Hoang LUONG ,  Hiroyuki TAKAHASHI ,  Akiteru KO ,  Asao YAMASHITA ,  Vaidyanathan BALASUBRAMANIAM ,  Takashi ENOMOTO ,  Daniel J. PRAGER

IPC分类号： H01L21/3065

CPC分类号： H01L21/32136 ,  H01J37/32091 ,  H01J37/32165 ,  H01J37/3266 ,  H01L21/823437 ,  H01L21/823456

摘要： A method for etching a differential metal gate structure on a substrate is described. The differential metal gate structure includes a metal gate layer overlying a high dielectric constant (high-k) dielectric layer, wherein the metal gate layer comprises a different thickness at different regions on the substrate. The metal gate layer is patterned by using a plasma etching process, wherein at least one etch step includes forming plasma using a halogen-containing gas and at least one etch step includes forming plasma using an additive gas having as atomic constituents C, H, and F.

摘要翻译： 描述了蚀刻基板上的差分金属栅极结构的方法。 差分金属栅极结构包括覆盖高介电常数（高k）电介质层的金属栅极层，其中金属栅极层在衬底上的不同区域包括不同的厚度。 通过使用等离子体蚀刻工艺对金属栅极层进行构图，其中至少一个蚀刻步骤包括使用含卤素气体形成等离子体，并且至少一个蚀刻步骤包括使用具有原子成分C，H和 F。