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    Method, apparatus and system for handling cache misses in a processor
    21.
    发明授权
    Method, apparatus and system for handling cache misses in a processor 有权
    用于处理处理器中的高速缓存未命中的方法，装置和系统

    公开(公告)号：US09405687B2

    公开(公告)日：2016-08-02

    申请号：US14070864

    申请日：2013-11-04

    Applicant: Intel Corporation

    Inventor： Bahaa Fahim ,  Samuel D. Strom ,  Vedaraman Geetha ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Krishnakumar Ganapathy ,  Cesar Maldonado

    IPC: G06F12/08

    CPC classification number: G06F12/0813 ,  G06F12/0831 ,  G06F12/0884 ,  G06F2212/2542 ,  Y02D10/13

    Abstract: In an embodiment, a processor includes one or more cores, and a distributed caching home agent (including portions associated with each core). Each portion includes a cache controller to receive a read request for data and, responsive to the data not being present in a cache memory associated with the cache controller, to issue a memory request to a memory controller to request the data in parallel with communication of the memory request to a home agent, where the home agent is to receive the memory request from the cache controller and to reserve an entry for the memory request. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括一个或多个核心和分布式缓存归属代理（包括与每个核心相关联的部分）。 每个部分包括高速缓存控制器，用于接收对数据的读取请求，并且响应于不存在于与高速缓存控制器相关联的高速缓冲存储器中的数据，向存储器控制器发出存储器请求以与 对归属代理的存储器请求，其中归属代理将从高速缓存控制器接收存储器请求并且为存储器请求保留条目。 描述和要求保护其他实施例。

    SCALABLY MECHANISM TO IMPLEMENT AN INSTRUCTION THAT MONITORS FOR WRITES TO AN ADDRESS
    22.
    发明申请
    SCALABLY MECHANISM TO IMPLEMENT AN INSTRUCTION THAT MONITORS FOR WRITES TO AN ADDRESS 审中-公开
    规范机制，以实施向地址写入的监视器的指令

    公开(公告)号：US20150095580A1

    公开(公告)日：2015-04-02

    申请号：US14040375

    申请日：2013-09-27

    Applicant: Intel Corporation

    Inventor： Yen-Cheng Liu ,  Bahaa Fahim ,  Erik G. Hallnor ,  Jeffrey D. Chamberlain ,  Stephen R. Van Doren ,  Antonio Juan

    IPC: G06F12/08

    Abstract: A processor includes a cache-side address monitor unit corresponding to a first cache portion of a distributed cache that has a total number of cache-side address monitor storage locations less than a total number of logical processors of the processor. Each cache-side address monitor storage location is to store an address to be monitored. A core-side address monitor unit corresponds to a first core and has a same number of core-side address monitor storage locations as a number of logical processors of the first core. Each core-side address monitor storage location is to store an address, and a monitor state for a different corresponding logical processor of the first core. A cache-side address monitor storage overflow unit corresponds to the first cache portion, and is to enforce an address monitor storage overflow policy when no unused cache-side address monitor storage location is available to store an address to be monitored.

    Abstract translation: 处理器包括对应于分布式高速缓存的第一高速缓存部分的高速缓存器侧地址监视器单元，其具有小于处理器的逻辑处理器总数的高速缓存器侧地址监视器存储位置的总数。 每个缓存侧地址监视器存储位置是存储要监视的地址。 核心侧地址监视器单元对应于第一核心，并且具有与第一核心的多个逻辑处理器相同数量的核心侧地址监视器存储位置。 每个核心侧地址监视器存储位置用于存储第一核心的不同对应逻辑处理器的地址和监视状态。 高速缓存侧地址监视器存储溢出单元对应于第一高速缓存部分，并且当没有未使用的高速缓存侧地址监视器存储位置可用于存储要监视的地址时，强制执行地址监视器存储溢出策略。

    Optimized caching agent with integrated directory cache
    25.
    发明授权
    Optimized caching agent with integrated directory cache 有权

    公开(公告)号：US10339060B2

    公开(公告)日：2019-07-02

    申请号：US15396174

    申请日：2016-12-30

    Applicant: Intel Corporation

    Inventor： Bahaa Fahim ,  Ashok Jagannathan ,  Jeffrey D. Chamberlain ,  Samuel D. Strom

    IPC: G06F12/0817 ,  G06F12/0831

    Abstract: System, method, and processor for enabling early deallocation of tracker entries which track memory accesses are described herein. One embodiment of a method includes: maintaining an RSF corresponding to a first processing unit of a plurality of processing units to track cache lines, wherein a cache line is tracked by the RSF if the cache line is stored in both a memory and one or more other processing unit, the memory is coupled to and shared by the plurality of processing units; receiving a request to access a target cache line from a processing core of the first processing unit; allocating a tracker entry corresponding to the request, the tracker entry used to track a status of the request; performing a lookup in the RSF for the target cache line; and deallocating the tracker entry responsive to a detection that the target cache line is not tracked the RSF.

    OPTIMIZED CACHING AGENT WITH INTEGRATED DIRECTORY CACHE
    27.
    发明申请
    OPTIMIZED CACHING AGENT WITH INTEGRATED DIRECTORY CACHE 审中-公开

    公开(公告)号：US20180189180A1

    公开(公告)日：2018-07-05

    申请号：US15396174

    申请日：2016-12-30

    Applicant: Intel Corporation

    Inventor： Bahaa Fahim ,  Ashok Jagannathan ,  Jeffrey D. Chamberlain ,  Samuel D. Strom

    IPC: G06F12/0815

    CPC classification number: G06F12/0833 ,  G06F12/0824 ,  G06F2212/1024 ,  G06F2212/1041

    Abstract: System, method, and processor for enabling early deallocation of tracker entries which track memory accesses are described herein. One embodiment of a method includes: maintaining an RSF corresponding to a first processing unit of a plurality of processing units to track cache lines, wherein a cache line is tracked by the RSF if the cache line is stored in both a memory and one or more other processing unit, the memory is coupled to and shared by the plurality of processing units; receiving a request to access a target cache line from a processing core of the first processing unit; allocating a tracker entry corresponding to the request, the tracker entry used to track a status of the request; performing a lookup in the RSF for the target cache line; and deallocating the tracker entry responsive to a detection that the target cache line is not tracked the RSF.

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