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    Approximate data bus inversion technique for latency sensitive applications
    23.
    发明授权
    Approximate data bus inversion technique for latency sensitive applications 有权

    公开(公告)号：US12117960B2

    公开(公告)日：2024-10-15

    申请号：US17029288

    申请日：2020-09-23

    Applicant: Intel Corporation

    Inventor： Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald S. Pasdast ,  Zuoguo Wu

    IPC: G06F13/42 ,  G06F13/40

    CPC classification number: G06F13/4291 ,  G06F13/4068 ,  G06F13/423

    Abstract: Systems, methods, and apparatuses associated with an approximate majority based data bus inversion technique are disclosed. A method comprises obtaining, at a first device connected by a plurality of lanes to a second device, original data comprising first bits and second bits, where the first bits are to be transmitted in a new clock cycle via first lanes of the plurality of lanes, and the second bits are to be transmitted in the new clock cycle via second lanes of the plurality of lanes. The method further includes determining whether a first criterion associated with the first bits is met, determining whether a second criterion associated with the second bits is met, and transmitting an inverted version of the original data via the plurality of lanes based, at least in part, on determining that the first criterion and the second criterion are met.

    ACTIVE DEVICE LAYER AT INTERCONNECT INTERFACES
    24.
    发明申请
    ACTIVE DEVICE LAYER AT INTERCONNECT INTERFACES 有权

    公开(公告)号：US20220399324A1

    公开(公告)日：2022-12-15

    申请号：US17344348

    申请日：2021-06-10

    Applicant: Intel Corporation

    Inventor： Han Wui Then ,  Adel A. Elsherbini ,  Kimin Jun ,  Johanna M. Swan ,  Shawna M. Liff ,  Sathya Narasimman Tiagaraj ,  Gerald S. Pasdast ,  Aleksandar Aleksov ,  Feras Eid

    IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00

    Abstract: A die assembly comprising: a first component layer having conductive through-connections in an insulator, a second component layer comprising a die, and an active device layer (ADL) at an interface between the first component layer and the second component layer. The ADL comprises active elements electrically coupled to the first component layer and the second component layer. The die assembly further comprises a bonding layer electrically coupling the ADL to the second component layer. In some embodiments, the die assembly further comprises another ADL at another interface between the first component layer and a package support opposite to the interface. The first component layer may comprise another die having through-substrate vias (TSVs). The die and the another die may be fabricated using different process nodes.

    Fast-lane routing for multi-chip packages
    26.
    发明授权
    Fast-lane routing for multi-chip packages 有权

    公开(公告)号：US11336559B2

    公开(公告)日：2022-05-17

    申请号：US16106926

    申请日：2018-08-21

    Applicant: Intel Corporation

    Inventor： Adel A. Elsherbini ,  Tejpal Singh ,  Shawna M. Liff ,  Gerald S. Pasdast ,  Johanna M. Swan

    IPC: H04L45/122 ,  H04L45/12 ,  H04L9/40 ,  G06F12/0842 ,  H04L49/109

    Abstract: Embodiments herein may relate to a processor package with a substrate and a multi-chip processor coupled with the substrate. The multi-chip processor may include a dual-sided interconnect structure coupled with a first chip, a second chip, and a third chip. The first chip may be communicatively coupled with the second chip by an on-chip communication route. Likewise, the second chip may be communicatively coupled with the first chip by an on-chip communication route. Additionally, the first chip may be communicatively coupled with the third chip by a fast-lane communication route. Other embodiments may be described and/or claimed.

    Valid lane training
    29.
    发明授权
    Valid lane training 有权

    公开(公告)号：US10461805B2

    公开(公告)日：2019-10-29

    申请号：US15761408

    申请日：2015-09-26

    Applicant: Intel Corporation

    Inventor： Venkatraman Iyer ,  Lip Khoon Teh ,  Mahesh Wagh ,  Zuoguo Wu ,  Azydee Hamid ,  Gerald S. Pasdast

    IPC: H04B3/40 ,  G06F13/20 ,  H04L25/03

    Abstract: One or more link training signals are received, including instances of a link training pattern, on a plurality of lanes of a physical link that includes at least one valid lane and a plurality of data lanes. The plurality of lanes are trained together using the link training signals to synchronize sampling of the valid lane with sampling of the plurality of data lanes. An active link state is entered and a valid signal received on the valid lane during the active link state. The valid signal includes a signal held at a value for a defined first duration and indicates that data is to be received on the plurality of data lanes in a second defined duration subsequent to the first duration. The data is to be received, during the active link state, on the plurality of data lanes during the second defined duration.

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