公开(公告)号：US20180174972A1

公开(公告)日：2018-06-21

申请号：US15386737

申请日：2016-12-21

Applicant: Intel Corporation

Inventor： Li-Sheng Weng ,  Chung-Hao Joseph Chen ,  Emile Davies-Venn ,  Kemal Aygun ,  Mitul B. Modi

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/66

Abstract: Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.

公开(公告)号：US09842832B2

公开(公告)日：2017-12-12

申请号：US15183179

申请日：2016-06-15

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  John S. Guzek ,  Johanna M. Swan ,  Christopher J. Nelson ,  Nitin A. Deshpande ,  William J. Lambert ,  Charles A. Gealer ,  Feras Eid ,  Islam A. Salama ,  Kemal Aygun ,  Sasha N. Oster ,  Tyler N. Osborn

IPC: H01L25/16 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H05K1/18

CPC classification number: H01L25/16 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/50 ,  H01L24/86 ,  H01L25/00 ,  H01L25/0655 ,  H01L2224/0405 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/29078 ,  H01L2224/86203 ,  H01L2224/86815 ,  H05K1/185 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.

公开(公告)号：US09807866B2

公开(公告)日：2017-10-31

申请号：US14954632

申请日：2015-11-30

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Adel Elsherbini ,  Robert L. Sankman ,  Kemal Aygun

IPC: H05K1/02 ,  H05K9/00 ,  H05K1/18

CPC classification number: H05K1/0216 ,  H01L23/552 ,  H05K1/025 ,  H05K1/181 ,  H05K3/284 ,  H05K2203/1322 ,  Y02P70/611

Abstract: An electronic package having a substrate that includes signal traces and ground traces; an electronic component mounted on an upper surface of the substrate such that the electronic component is electrically connected to the signal traces and the ground traces in the substrate; an insulating layer covering the electronic component and the upper surface of the substrate; and an electromagnetic interference shielding mold covering the insulation layer such that the electromagnetic interference shielding mold is electrically connected to the ground traces in the substrate. In some forms of the electronic package, the electromagnetic interference shielding mold is electrically connected to the ground traces through openings in the insulation layer.

公开(公告)号：US09564407B2

公开(公告)日：2017-02-07

申请号：US15187737

申请日：2016-06-20

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Tolga Memioglu ,  Tao Wu ,  Kemal Aygun

IPC: H01L23/48 ,  H05K1/11 ,  H01L23/52 ,  H01L23/66 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L23/50 ,  H01L25/18 ,  H01P3/08 ,  H05K1/02

CPC classification number: H01L23/66 ,  H01L21/76877 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/18 ,  H01L2223/6627 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2924/01029 ,  H01L2924/1426 ,  H01L2924/143 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01P3/081 ,  H05K1/0216 ,  H05K1/0222 ,  H05K1/0228 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane. In embodiments, mutual capacitance is tuned relative to self-capacitance to reverse polarity of far end crosstalk between a victim and aggressor channel relative to that induced by other interconnect portions along the length of the channels, such as inductively coupled portions. In embodiments, a transmission line for a single-ended channel includes a material of a higher dielectric constant within the same routing plane as a microstrip or stripline conductor, and a material of a lower dielectric constant between the conductor and the ground plane(s). In embodiments, a transmission line for a differential pair includes a material of a lower dielectric constant within the same routing plane as a microstrip or stripline conductors, and a material of a higher dielectric constant between the conductors and the ground plane(s).

Abstract translation: 具有分离信号迹线的第一介电材料的传输线和将信号迹线与接地平面分开的第二介电材料。 在实施例中，互电容相对于自电容被调谐，以相对于沿着诸如电感耦合部分的通道的长度的其它互连部分感应到的远端串扰的极性反转。 在实施例中，用于单端通道的传输线包括在与微带线或带状线导体相同的布线平面内具有较高介电常数的材料，以及在导体和接地平面之间具有较低介电常数的材料， 。 在实施例中，用于差分对的传输线包括在与微带线或带状线导体相同的布线平面内具有较低介电常数的材料，以及在导体和接地平面之间具有较高介电常数的材料。

公开(公告)号：US20160300824A1

公开(公告)日：2016-10-13

申请号：US15183179

申请日：2016-06-15

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  John S. Guzek ,  Johanna M. Swan ,  Christopher J. Nelson ,  Nitin A. Deshpande ,  William J. Lambert ,  Charles A. Gealer ,  Feras Eid ,  Islam A. Salama ,  Kemal Aygun ,  Sasha N. Oster ,  Tyler N. Osborn

IPC: H01L25/16 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/16 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/50 ,  H01L24/86 ,  H01L25/00 ,  H01L25/0655 ,  H01L2224/0405 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/29078 ,  H01L2224/86203 ,  H01L2224/86815 ,  H05K1/185 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.

公开(公告)号：US20160268710A1

公开(公告)日：2016-09-15

申请号：US14642078

申请日：2015-03-09

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Gaurav Chawla ,  Rajasekaran Swaminathan ,  Kemal Aygun ,  Li Sun

IPC: H01R12/70 ,  H01R43/20

CPC classification number: H01R12/7076 ,  H01R43/205 ,  H05K7/1038

Abstract: Embodiments of the present disclosure are directed towards a snap connector for socket assembly and associated techniques and configurations. In one embodiment, a socket assembly includes a socket body having a plurality of openings extending from a first side of the socket body to a second side of the socket body to provide an electrical pathway between the first side and the second side, the second side disposed opposite to the first side, wherein a holding portion of an individual opening of the plurality of openings adjacent to the first side of the socket body is shaped to hold a corresponding electrical contact of a die package by elastic force applied by the socket body to the electrical contact when the electrical contact is positioned within the holding portion. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于插座组件和相关技术和配置的卡扣连接器。 在一个实施例中，插座组件包括插座主体，该插座主体具有从插座本体的第一侧延伸到插座主体的第二侧的多个开口，以在第一侧和第二侧之间提供电路径，第二侧 与所述第一侧相对设置，其中所述多个开口的与所述插座主体的第一侧相邻的开口的保持部分成形为通过由所述插座主体施加的弹力来保持模具组件的对应电接触， 当电触点位于保持部分内时的电接触。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09391018B2

公开(公告)日：2016-07-12

申请号：US14171714

申请日：2014-02-03

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Tolga Memioglu ,  Tao Wu ,  Kemal Aygun

IPC: H01L21/768 ,  H01L23/522 ,  H01F5/04 ,  H01F27/28 ,  H01L23/498 ,  H01L23/66 ,  H01L23/00

CPC classification number: H01L23/66 ,  H01L21/76877 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/18 ,  H01L2223/6627 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2924/01029 ,  H01L2924/1426 ,  H01L2924/143 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01P3/081 ,  H05K1/0216 ,  H05K1/0222 ,  H05K1/0228 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane. In embodiments, mutual capacitance is tuned relative to self-capacitance to reverse polarity of far end crosstalk between a victim and aggressor channel relative to that induced by other interconnect portions along the length of the channels, such as inductively coupled portions. In embodiments, a transmission line for a single-ended channel includes a material of a higher dielectric constant within the same routing plane as a microstrip or stripline conductor, and a material of a lower dielectric constant between the conductor and the ground plane(s). In embodiments, a transmission line for a differential pair includes a material of a lower dielectric constant within the same routing plane as a microstrip or stripline conductors, and a material of a higher dielectric constant between the conductors and the ground plane(s).

Abstract translation: 具有分离信号迹线的第一介电材料的传输线和将信号迹线与接地平面分开的第二介电材料。 在实施例中，互电容相对于自电容被调谐，以相对于沿着诸如电感耦合部分的通道的长度的其它互连部分感应到的远端串扰的极性反转。 在实施例中，用于单端通道的传输线包括在与微带线或带状线导体相同的布线平面内具有较高介电常数的材料，以及在导体和接地平面之间具有较低介电常数的材料， 。 在实施例中，用于差分对的传输线包括在与微带线或带状线导体相同的布线平面内具有较低介电常数的材料，以及在导体和接地平面之间具有较高介电常数的材料。

公开(公告)号：US20230420377A1

公开(公告)日：2023-12-28

申请号：US17847257

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Cemil Geyik ,  Kemal Aygun ,  Zhiguo Qian ,  Kristof Kuwawi Darmawikarta ,  Zhichao Zhang

IPC: H01L23/538 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/5386 ,  H01L25/0652 ,  H01L25/0655 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L24/16

Abstract: Embodiments of a microelectronic assembly comprise: a package substrate comprising a conductive trace in a dielectric material, the conductive trace surrounded by a conductive structure coupled to a ground connection, the package substrate further comprising metallization layers alternating with dielectric layers of the dielectric material; and an integrated circuit (IC) die coupled to a surface of the package substrate, the IC die being coupled to the conductive trace by a conductive pathway. The dielectric layers and the metallization layers are parallel to the surface of the package substrate, the conductive trace comprises a trench via in one of the dielectric layers, and the conductive structure comprises grounded plates extending across a length and width of the package substrate in metallization layers on either side of the dielectric layer.

公开(公告)号：US11810859B2

公开(公告)日：2023-11-07

申请号：US16793951

申请日：2020-02-18

Applicant: INTEL CORPORATION

Inventor： Srinivas V. Pietambaram ,  Rahul N. Manepalli ,  Cemil S. Geyik ,  Kemal Aygun

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53295 ,  H01L21/76832 ,  H01L21/76834

Abstract: Structures are described that include multi-layered adhesion promotion films over a conductive structure in a microelectronic package. The multi-layered aspect provides adhesion to surrounding dielectric material without a roughened surface of the conductive structure. Furthermore, the multi-layered aspect allows for materials with different dielectric constants to be used, the average of which can provide a closer match to the dielectric constant of the surrounding dielectric material. According to an embodiment, a first dielectric layer that includes at least one nitride material can provide good adhesion with the underlying conductive structure, while one or more subsequent dielectric layers that include at least one oxide material can provide different dielectric constant values (e.g., typically lower) compared to the first dielectric layer to bring the overall dielectric constant closer to that of a surrounding dielectric material. The first and second layers may be discrete layers or a single continuous layer with grading.

公开(公告)号：US20230352416A1

公开(公告)日：2023-11-02

申请号：US17733170

申请日：2022-04-29

Applicant: Intel Corporation

Inventor： Cemil Geyik ,  Kemal Aygun ,  Yidnekachew Mekonnen ,  Zhichao Zhang ,  Suddhasattwa Nad

IPC: H01L23/538

CPC classification number: H01L23/5386 ,  H01L24/16

Abstract: Methods, apparatus, systems, and articles of manufacture to improve signal integrity performance in integrated circuit packages are disclosed. An integrated circuit (IC) package includes a substrate; a first conductive pad in a first metal layer in the substrate; and a second conductive pad in a second metal layer in the substrate. The first metal layer is adjacent the second metal layer with no intervening metal layers therebetween. The integrated circuit (IC) package further includes a conductive protrusion extending from the first conductive pad toward the second conductive pad.