公开(公告)号：US10210066B2

公开(公告)日：2019-02-19

申请号：US14998047

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Bret L. Toll ,  Konrad K. Lai ,  Matthew C. Merten ,  Martin G. Dixon

IPC: G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F11/28 ,  G06F9/46 ,  G06F9/30 ,  G06F12/0811 ,  G06F9/38 ,  G11C7/10 ,  G06F11/22 ,  G06F12/0897 ,  G06F12/0817 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F11/14 ,  G06F11/25

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

公开(公告)号：US10152401B2

公开(公告)日：2018-12-11

申请号：US14977659

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Bret L. Toll ,  Konrad K. Lai ,  Matthew C. Merten ,  Martin G. Dixon

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F11/28 ,  G06F9/46 ,  G06F9/30 ,  G06F12/0811 ,  G06F9/38 ,  G11C7/10 ,  G06F11/22 ,  G06F11/263 ,  G06F12/0897 ,  G06F12/0817 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F11/14 ,  G06F11/25

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

公开(公告)号：US09965375B2

公开(公告)日：2018-05-08

申请号：US15194881

申请日：2016-06-28

Applicant: INTEL CORPORATION

Inventor： Matthew C. Merten ,  Beeman C. Strong ,  Michael W. Chynoweth ,  Grant G. Zhou ,  Andreas Kleen ,  Kimberly C. Weier ,  Angela D. Schmid ,  Stanislav Bratanov ,  Seth Abraham ,  Jason W. Brandt ,  Ahmad Yasin

IPC: G06F11/36 ,  G06F9/455 ,  H04L12/26 ,  H04L12/24

CPC classification number: G06F11/3636 ,  G06F9/45558 ,  G06F2009/45591 ,  H04L41/0613 ,  H04L43/04

Abstract: A core includes a memory buffer and executes an instruction within a virtual machine. A processor tracer captures trace data and formats the trace data as trace data packets. An event-based sampler generates field data for a sampling record in response to occurrence of an event of a certain type as a result of execution of the instruction. The processor tracer, upon receipt of the field data: formats the field data into elements of the sampling record as a group of record packets; inserts the group of record packets between the trace data packets as a combined packet stream; and stores the combined packet stream in the memory buffer as a series of output pages. The core, when in guest profiling mode, executes a virtual machine monitor to map output pages of the memory buffer to host physical pages of main memory using multilevel page tables.

公开(公告)号：US09495159B2

公开(公告)日：2016-11-15

申请号：US14040016

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Mark J. Dechene ,  Srikanth T. Srinivasan ,  Matthew C. Merten ,  Tong Li ,  Christine E. Wang

IPC: G06F9/30 ,  G06F9/46

CPC classification number: G06F9/30145 ,  G06F8/445 ,  G06F8/47 ,  G06F9/30123 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/45508 ,  G06F9/461

Abstract: In response to detecting one or more conditions are met, a checkpoint of a current state of a thread may be created. One or more incomplete instructions may be moved from a first level of a re-order buffer to a second level of the re-order buffer. Each incomplete instruction may be currently executing or awaiting execution.

Abstract translation: 响应于检测到一个或多个条件被满足，可以创建线程的当前状态的检查点。 可以将一个或多个不完整的指令从重新排序缓冲器的第一级移动到重新排序缓冲器的第二级。 每个不完整的指令可能正在执行或等待执行。

公开(公告)号：US20230315501A1

公开(公告)日：2023-10-05

申请号：US17711770

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Sebastian Winkel ,  Rangeen Basu Roy Chowdhury ,  Matthew C. Merten ,  Jason M. Agron ,  Tyler N. Sondag ,  Gregory A. Woods

IPC: G06F9/455

CPC classification number: G06F9/4552 ,  G06F9/45525

Abstract: Systems, methods, and devices for original code emulation for performance monitoring is provided. A system may memory to store instructions. A processor may implement an instruction converter in hardware or software to convert the instructions to translated code. Specifically, the instruction converter receives the instructions and translates the stored instructions into the translated code that includes one or more indexed instructions. The one or more indexed instructions include a field indicating a number of branches in the stored instructions that are taken in the translated code.

公开(公告)号：US20220027154A1

公开(公告)日：2022-01-27

申请号：US17496632

申请日：2021-10-07

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Matthew C. Merten ,  Tong Li ,  Bret T. Toll, I

IPC: G06F9/30 ,  G06F9/38

Abstract: A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

公开(公告)号：US20200242003A1

公开(公告)日：2020-07-30

申请号：US16699871

申请日：2019-12-02

Applicant: Intel Corporation

Inventor： Matthew C. Merten ,  Beeman C. Strong ,  Michael W. Chynoweth ,  Grant G. Zhou ,  Andreas Kleen ,  Kimberly C. Weier ,  Angela D. Schmid ,  Stanislav Bratanov ,  Seth Abraham ,  Jason W. Brandt ,  Ahmad Yasin

IPC: G06F11/36 ,  G06F9/455

Abstract: A processor is to execute and retire instructions for a virtual machine. A reload register is coupled to the core is to store a reload value. A performance monitoring counter (PMC) register is coupled to the reload register and an event-based sampler operatively is coupled to the reload register and the PMC register. The event-based sampler includes circuitry to load the reload value into the PMC register and increment the PMC register after detecting each occurrence of an event of a certain type as a result of execution of the instructions. Upon detecting an occurrence of the event after the PMC register reaches a predetermined trigger value, the event-based sampler is to execute microcode to generate field data for elements within a sampling record, wherein the field data relates to a current processor state of execution, and reload the reload value from the reload register into the PMC register.

公开(公告)号：US20190188115A1

公开(公告)日：2019-06-20

申请号：US16284581

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Beeman C. Strong ,  Matthew C. Merten ,  Lee W. Baugh

IPC: G06F11/36 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0875

CPC classification number: G06F11/3648 ,  G06F9/3004 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3877 ,  G06F11/3476 ,  G06F11/3636 ,  G06F12/0875 ,  G06F2212/452

Abstract: There is disclosed in an example a processor, having: a front end including circuitry to decode instructions from an instruction stream; a data cache unit including circuitry to cache data for the processor; and a core triggering block (CTB) to provide integration between two or more different debug capabilities.

公开(公告)号：US20160203068A1

公开(公告)日：2016-07-14

申请号：US14998052

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Bret L. Toll ,  Konrad K. Lai ,  Matthew C. Merten ,  Martin G. Dixon

IPC: G06F11/263 ,  G06F9/38 ,  G06F9/30 ,  G06F12/08 ,  G06F11/22

CPC classification number: G06F11/28 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/466 ,  G06F9/467 ,  G06F11/1407 ,  G06F11/2236 ,  G06F11/25 ,  G06F11/263 ,  G06F12/0811 ,  G06F12/0828 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/1032 ,  G06F2212/20 ,  G06F2212/283 ,  G06F2212/314 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/608 ,  G06F2212/621 ,  G11C7/1072

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

公开(公告)号：US20160026464A1

公开(公告)日：2016-01-28

申请号：US14811552

申请日：2015-07-28

Applicant: Intel Corporation

Inventor： Laura A. Knauth ,  Matthew C. Merten ,  Ronak Singhal ,  Hugh M. Caffrey

IPC: G06F9/30

CPC classification number: G06F9/3013 ,  G06F9/30109 ,  G06F9/30112 ,  G06F11/3409 ,  G06F11/3466 ,  G06F2201/88

Abstract: A processor includes one or more execution units to execute instructions, each having one or more elements in different element sizes using one or more registers in different register sizes. The processor further includes a counter configured to count a number of instructions performing predetermined types of operations executed by the one or more execution units. The processor further includes one or more registers to allow an external component to configure the counter to count a number of instructions associated with a combination of a register size and a element size (register/element size) and to retrieve a counter value produced by the counter.

Abstract translation: 处理器包括执行指令的一个或多个执行单元，每个执行单元具有使用不同寄存器大小的一个或多个寄存器的不同元件大小的一个或多个元件。 处理器还包括计数器，其被配置为对执行由一个或多个执行单元执行的预定类型的操作的多个指令进行计数。 处理器还包括一个或多个寄存器，以允许外部组件配置计数器以对与寄存器大小和元素大小（寄存器/元素大小）的组合相关联的多个指令进行计数，并且检索由 计数器。