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    Managing disturbance induced errors
    22.
    发明授权
    Managing disturbance induced errors 有权
    管理扰动引起的错误

    公开(公告)号：US09202547B2

    公开(公告)日：2015-12-01

    申请号：US13832278

    申请日：2013-03-15

    Applicant: Intel Corporation

    Inventor： Prashant S. Damle ,  Frank T. Hady ,  Paul D. Ruby ,  Kiran Pangal ,  Sowmiya Jayachandran

    IPC: G06F12/16 ,  G11C11/406 ,  G11C16/34

    CPC classification number: G11C7/1072 ,  G11C11/406 ,  G11C11/40618 ,  G11C16/3431

    Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.

    Abstract translation: 在一个实施例中，存储器控制器可以确定与存储器件中的目标存储器单元相关联的一个或多个相邻存储器单元将被刷新。 控制器可以生成与刷新一个或多个相邻存储器单元相关联的命令。 控制器可以将命令从存储器控制器传送到包含目标存储器单元的存储器件。 命令可以指示存储器设备刷新相邻存储器单元和/或返回与相邻存储器单元相关联的一个或多个地址。

    VELOCITY BASED WRITE DISTURB REFRESH
    23.
    发明申请
    VELOCITY BASED WRITE DISTURB REFRESH 有权

    公开(公告)号：US20220382465A1

    公开(公告)日：2022-12-01

    申请号：US17818161

    申请日：2022-08-08

    Applicant: Intel Corporation

    Inventor： Rakan Maddah ,  Jason Gayman ,  Arjun Kripanidhi ,  Wilson Fang ,  Prashant S. Damle

    IPC: G06F3/06

    Abstract: Systems, apparatuses and methods may provide for technology that determines a write-to-write delay with respect to a memory cell, wherein one or more neighboring cells are adjacent to the memory cell and controls a write disturb refresh rate of the one or more neighboring cells based on the write-to-write delay. In one example, the technology increments a write counter corresponding to the memory cell by a first value if the write-to-write delay exceeds a delay threshold and increments the write counter by a second value if the write-to-write delay does not exceed the delay threshold, wherein the second value is greater than the first value, and wherein the write disturb refresh rate is controlled based on the write counter.

    TIME TRACKING WITH PATROL SCRUB
    27.
    发明申请
    TIME TRACKING WITH PATROL SCRUB 审中-公开

    公开(公告)号：US20190102320A1

    公开(公告)日：2019-04-04

    申请号：US15721379

    申请日：2017-09-29

    Applicant: INTEL CORPORATION

    Inventor： Philip Hillier ,  Jeffrey W. Ryden ,  Muthukumar P. Swaminathan ,  Zion S. Kwok ,  Kunal A. Khochare ,  Richard P. Mangold ,  Prashant S. Damle

    IPC: G06F12/126 ,  G06F12/02 ,  G11C7/22

    Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller memory; a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a current timer index from a timer circuitry in response to an initiation of a periodic patrol scrub and to compare the current timer index to a stored timestamp. The VDM selection circuitry is to update a state of a sub-block of a memory array, if the state is less than a threshold and a difference between the current timer index and the stored timestamp is nonzero. The timestamp circuitry is further to store the current timer index as a new timestamp.

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