公开(公告)号：US20210151566A1

公开(公告)日：2021-05-20

申请号：US16683894

申请日：2019-11-14

Applicant: International Business Machines Corporation

Inventor： Jingyun Zhang ,  Takashi Ando ,  Choonghyun Lee

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/267

Abstract: A semiconductor device and method of forming the same including a plurality of vertically aligned semiconductor channel layers disposed above a substrate layer, a gate stack formed on, and around the vertically aligned semiconductor channel layers and source and drain elements disposed in contact with sidewalls of the vertically aligned semiconductor channel layers. An uppermost vertically aligned semiconductor channel layer has a first thickness of semiconductor material and the remaining vertically aligned semiconductor channel layers have a second thickness of semiconductor material different from the first thickness.

公开(公告)号：US10991537B2

公开(公告)日：2021-04-27

申请号：US16402302

申请日：2019-05-03

Applicant: International Business Machines Corporation

Inventor： Injo Ok ,  Choonghyun Lee ,  Soon-Cheon Seo ,  Seyoung Kim

IPC: H01J21/10 ,  H01J9/02 ,  H01J9/28 ,  H01J19/24

Abstract: A vertical vacuum transistor with a sharp tip structure, and associated fabrication process, is provided that is compatible with current vertical CMOS fabrication processing. The resulting vertical vacuum channel transistor advantageously provides improved operational characteristics including a higher operating frequency, a higher power output, and a higher operating temperature while at the same time providing a higher density of vertical transistor devices during the manufacturing process.

公开(公告)号：US20210119019A1

公开(公告)日：2021-04-22

申请号：US17136548

申请日：2020-12-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Shogo Mochizuki ,  Choonghyun Lee ,  Juntao Li

IPC: H01L29/66 ,  H01L21/768 ,  H01L23/535 ,  H01L21/225 ,  H01L21/324 ,  H01L29/08 ,  H01L29/78

Abstract: A method of forming a fin field effect device is provided. The method includes forming one or more vertical fins on a substrate and a fin template on each of the vertical fins. The method further includes forming a gate structure on at least one of the vertical fins, and a top spacer layer on the at least one gate structure, wherein at least an upper portion of the at least one of the one or more vertical fins is exposed above the top spacer layer. The method further includes forming a top source/drain layer on the top spacer layer and the exposed upper portion of the at least one vertical fin. The method further includes forming a sacrificial spacer on opposite sides of the fin templates and the top spacer layer, and removing a portion of the top source/drain layer not covered by the sacrificial spacer to form a top source/drain electrically connected to the vertical fins.

公开(公告)号：US10943903B2

公开(公告)日：2021-03-09

申请号：US16590976

申请日：2019-10-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Choonghyun Lee ,  Jingyun Zhang ,  Takashi Ando ,  Alexander Reznicek ,  Pouya Hashemi

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L21/02 ,  H01L21/28 ,  H01L29/167 ,  H01L29/08 ,  H01L29/78 ,  H01L29/10 ,  H01L29/49 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/324

Abstract: A method is presented for triggering asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET). The method includes constructing a first set fins from a first material, constructing a second set of fins from a second material, forming a source region between the first set of fins, and forming a drain region between the second set of fins, the source region composed of a different material than the drain region. The method further includes depositing a first high-k metal gate over the first set of fins and depositing a second high-k metal gate over the second set of fins, the second high-k metal gate being different than the first high-k metal gate such that the asymmetric threshold voltage is present along the channel of the VTFET in a region defined at the bottom of the first and second set of fins.

公开(公告)号：US10943787B2

公开(公告)日：2021-03-09

申请号：US16287322

申请日：2019-02-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jingyun Zhang ,  Choonghyun Lee ,  Takashi Ando ,  Alexander Reznicek ,  Pouya Hashemi

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/285 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/06

Abstract: A method of forming a nanosheet field effect transistor device is provided. The method includes forming a stack of alternating sacrificial layer segments and nanosheet layer segments on a substrate. The method further includes removing the sacrificial layer segments to form channels on opposite sides of the nanosheet layer segments. The method further includes depositing a gate dielectric layer around each of the nanosheet layer segments, and forming a work function material block on the gate dielectric layer to form a gate-all-around structure on the nanosheet layer segments. The method further includes forming a capping layer on the work function material block.

公开(公告)号：US10937862B2

公开(公告)日：2021-03-02

申请号：US16050735

申请日：2018-07-31

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Choonghyun Lee ,  Xin Miao ,  Jingyun Zhang

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/08 ,  H01L23/532 ,  H01L29/66 ,  H01L29/423 ,  H01L21/764

Abstract: Parasitic transistor formation under a semiconductor containing nanosheet device is eliminated by forming an airgap between the source/drain regions of the semiconductor containing nanosheet device and the semiconductor substrate. The airgap is created by forming a sacrificial germanium-containing semiconductor material at the bottom of the source/drain regions prior to the epitaxial growth of the source/drain regions from physically exposed sidewalls of each semiconductor channel material nanosheet of a nanosheet material stack. After inner dielectric spacer formation, the sacrificial germanium-containing semiconductor material can be reflown to seal any possible openings to the semiconductor substrate. The source/drain regions are then epitaxially grown and thereafter, the sacrificial germanium-containing semiconductor material is removed from the structure creating the airgap between the source/drain regions of the semiconductor containing nanosheet device and the semiconductor substrate.

公开(公告)号：US10896965B2

公开(公告)日：2021-01-19

申请号：US16692809

申请日：2019-11-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Adra Carr ,  Jingyun Zhang ,  Choonghyun Lee ,  Takashi Ando ,  Pouya Hashemi

IPC: H01L29/786 ,  H01L29/417 ,  H01L21/768 ,  H01L21/285 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45

Abstract: A method of forming a source/drain contact is provided. The method includes forming a sacrificial layer on a source/drain, and depositing an oxidation layer on the sacrificial layer. The method further includes heat treating the oxidation layer and the sacrificial layer to form a modified sacrificial layer. The method further includes forming a protective liner on the modified sacrificial layer, and depositing an interlayer dielectric layer on the protective liner. The method further includes forming a trench in the interlayer dielectric layer that exposes a portion of the protective liner.

公开(公告)号：US10892325B2

公开(公告)日：2021-01-12

申请号：US16455096

申请日：2019-06-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Juntao Li ,  Kangguo Cheng ,  Choonghyun Lee ,  Peng Xu

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: A method of forming a fin field effect transistor device is provided. The method includes forming a vertical fin layer on a bottom source/drain layer, and forming one or more fin templates on the vertical fin layer. The method further includes forming a vertical fin below each of the one or more fin templates. The method further includes reducing the width of each of the vertical fins to form one or more thinned vertical fins, wherein at least a portion of the fin template overhangs the sides of the underlying thinned vertical fin. The method further includes depositing a bottom spacer layer on the bottom source/drain layer, wherein the bottom spacer layer has a non-uniform thickness that tapers in a direction towards the thinned vertical fins.

公开(公告)号：US10886376B2

公开(公告)日：2021-01-05

申请号：US16692741

申请日：2019-11-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Adra Carr ,  Jingyun Zhang ,  Choonghyun Lee ,  Takashi Ando ,  Pouya Hashemi

IPC: H01L29/417 ,  H01L29/786 ,  H01L21/768 ,  H01L21/285 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45

Abstract: A method of forming a source/drain contact is provided. The method includes forming a sacrificial layer on a source/drain, and depositing an oxidation layer on the sacrificial layer. The method further includes heat treating the oxidation layer and the sacrificial layer to form a modified sacrificial layer. The method further includes forming a protective liner on the modified sacrificial layer, and depositing an interlayer dielectric layer on the protective liner. The method further includes forming a trench in the interlayer dielectric layer that exposes a portion of the protective liner.

公开(公告)号：US20200381520A1

公开(公告)日：2020-12-03

申请号：US16425165

申请日：2019-05-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Alexander Reznicek ,  Jingyun Zhang ,  Choonghyun Lee ,  Pouya Hashemi

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02

Abstract: Semiconductor devices and methods of forming the same include forming an inner spacer on a semiconductor fin. Two outer spacers are formed around the inner spacer, with one outer spacer being in contact with the inner spacer and with the other outer spacer being separated from the inner spacer by a gap. A dipole-forming layer is formed on the semiconductor fin in the gap. The inner spacer is etched away. A gate stack is formed on the semiconductor fin, between the outer spacers.