公开(公告)号：US20170221708A1

公开(公告)日：2017-08-03

申请号：US15008615

申请日：2016-01-28

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  Jeffrey C. Shearer ,  John R. Sporre ,  Sean Teehan

IPC: H01L21/02 ,  H01L21/306 ,  H01L29/16 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/02603 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.

公开(公告)号：US09362179B1

公开(公告)日：2016-06-07

申请号：US14746223

申请日：2015-06-22

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ryan O. Jung ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L21/8238 ,  H01L21/322 ,  H01L21/308 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/161

CPC classification number: H01L27/0924 ,  H01L21/3081 ,  H01L21/3221 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A silicon fin precursor is formed in an nFET device region and a fin stack comprising alternating material portions, and from bottom to top, of silicon and a silicon germanium alloy is formed in a pFET device region. A thermal anneal is then used to convert the fin stack into a silicon germanium alloy fin precursor. A thermal oxidation process follows that converts the silicon fin precursor into a silicon fin and the silicon germanium alloy fin precursor into a silicon germanium alloy fin. Functional gate structures can be formed straddling over each of the various fins.

Abstract translation: 在nFET器件区域中形成硅鳍前体，并且在pFET器件区域中形成包括硅的交替材料部分以及从底部到顶部的硅和硅锗合金的鳍片堆叠。 然后使用热退火将翅片叠层转换成硅锗合金翅片前体。 热氧化工艺之后，将硅翅片前体转化成硅翅片，将硅锗合金翅片前体转化成硅锗合金翅片。 功能门结构可跨越各个翅片跨越形成。

公开(公告)号：US11315922B2

公开(公告)日：2022-04-26

申请号：US16807731

申请日：2020-03-03

Applicant: International Business Machines Corporation

Inventor： Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Sivananda K. Kanakasabapathy ,  John R. Sporre

IPC: H01L29/165 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L21/8238 ,  H01L27/092

Abstract: The present invention provides fin cut techniques in a replacement gate process for finFET fabrication. In one aspect, a method of forming a finFET employs a dummy gate material to pin a lattice constant of patterned fins prior to a fin cut thereby preventing strain relaxation. A dielectric fill in a region of the fin cut (below the dummy gates) reduces an aspect ratio of dummy gates formed from the dummy gate material in the fin cut region, thereby preventing collapse of the dummy gates. FinFETs formed using the present process are also provided.

公开(公告)号：US10741752B2

公开(公告)日：2020-08-11

申请号：US16734922

申请日：2020-01-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony J. Annunziata ,  Babar A. Khan ,  Chandrasekharan Kothandaraman ,  John R. Sporre

IPC: H01L43/12 ,  G11C11/16 ,  H01L43/08 ,  H01L27/22

Abstract: Methods of forming the MRAM generally include forming an array of MTJ having sub-lithographic dimensions. The array can be formed by providing a substrate including a MTJ material stack including a reference ferromagnetic layer, a tunnel barrier layer, and a free ferromagnetic layer on an opposite side of the tunnel barrier layer. A hardmask layer is deposited onto the MTJ material stack. A first sidewall spacer is formed on the hardmask layer in a first direction. A second sidewall spacer is formed over the first sidewall in a second direction, wherein the first direction is orthogonal to the second direction. The second sidewall spacer intersects the first sidewall spacer. The first sidewall spacer is processed using the second sidewall spacer as mask to form a pattern of oxide pillars having sub-lithographic dimensions. The pattern of oxide pillars are transferred into the MTJ stack to form the array.

公开(公告)号：US20200219874A1

公开(公告)日：2020-07-09

申请号：US16807731

申请日：2020-03-03

Applicant: International Business Machines Corporation

Inventor： Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Sivananda K. Kanakasabapathy ,  John R. Sporre

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L21/8238 ,  H01L27/092

Abstract: The present invention provides fin cut techniques in a replacement gate process for finFET fabrication. In one aspect, a method of forming a finFET employs a dummy gate material to pin a lattice constant of patterned fins prior to a fin cut thereby preventing strain relaxation. A dielectric fill in a region of the fin cut (below the dummy gates) reduces an aspect ratio of dummy gates formed from the dummy gate material in the fin cut region, thereby preventing collapse of the dummy gates. FinFETs formed using the present process are also provided.

公开(公告)号：US10658473B2

公开(公告)日：2020-05-19

申请号：US16033786

申请日：2018-07-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Andrew M. Greene ,  John R. Sporre ,  Peng Xu

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/775

Abstract: Semiconductor devices include a first dielectric layer formed over a source and drain region. A second dielectric layer is formed over the first dielectric layer, the second dielectric layer having a flat, non-recessed top surface. A gate stack passes vertically through the first and second dielectric layers to contact the source and drain regions and an underlying substrate.

公开(公告)号：US20200066519A1

公开(公告)日：2020-02-27

申请号：US16671686

申请日：2019-11-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Muthumanickam Sankarapandian ,  Soon-Cheon Seo ,  Indira P. Seshadri ,  John R. Sporre

IPC: H01L21/033 ,  H01L21/8238 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/311

Abstract: A method for semiconductor processing includes removing, from a first region of a semiconductor device, a middle layer and a bottom layer of a trilayer structure including a photoresist layer to expose at least one first structure. A top layer of the trilayer structure in a second region of the semiconductor device is removed during the removal of the bottom layer in the first region. The method further includes, after removing the middle and bottom layers in the first region, filling the first region to protect the at least one first structure.

公开(公告)号：US20190341490A1

公开(公告)日：2019-11-07

申请号：US16516477

申请日：2019-07-19

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/78 ,  H03K17/687 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/786

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

公开(公告)号：US10424663B2

公开(公告)日：2019-09-24

申请号：US15813523

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H03K17/687 ,  H01L29/786 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

公开(公告)号：US10396181B2

公开(公告)日：2019-08-27

申请号：US16047042

申请日：2018-07-27

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  Jeffrey C. Shearer ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/306 ,  H01L29/16 ,  H01L29/78 ,  H01L29/40 ,  H01L29/775

Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.