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258 条记录 (耗时 0.029 秒)

    Sacrificial shorting straps for superconducting qubits
    23.
    发明授权
    Sacrificial shorting straps for superconducting qubits 有权

    公开(公告)号：US09705063B2

    公开(公告)日：2017-07-11

    申请号：US14749157

    申请日：2015-06-24

    申请人： International Business Machines Corporation

    发明人： Josephine B. Chang ,  Douglas T. McClure, III

    IPC分类号： H01L39/22 ,  H01L39/24 ,  H01L39/02

    CPC分类号： H01L21/3065 ,  H01L29/66977 ,  H01L39/025 ,  H01L39/223 ,  H01L39/2493

    摘要： A technique relates to protecting a tunnel junction. A first electrode paddle and a second electrode paddle are on a substrate. The first and second electrode paddles oppose one another. A sacrificial shorting strap is formed on the substrate. The sacrificial shorting strap connects the first electrode paddle and the second electrode paddle; The tunnel junction is formed connecting the first electrode paddle and the second electrode paddle, after forming the sacrificial shorting strap. The substrate is mounted on a portion of a quantum cavity. The portion of the quantum cavity is placed in a vacuum chamber. The sacrificial shorting strap is etched away in the vacuum chamber while the substrate is mounted to the portion of the quantum cavity, such that the sacrificial shorting strap no longer connects the first and second electrode paddles. The tunnel junction has been protected from electrostatic discharge by the sacrificial shorting strap.

    III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology
    26.
    发明授权
    III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology 有权
    III-V，SiGe或Ge基极双极晶体管和CMOS混合技术

    公开(公告)号：US09496184B2

    公开(公告)日：2016-11-15

    申请号：US14245627

    申请日：2014-04-04

    申请人： International Business Machines Corporation

    发明人： Josephine B. Chang ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

    IPC分类号： H01L21/8238 ,  H01L21/8249 ,  H01L29/66 ,  H01L21/24 ,  H01L29/10 ,  H01L29/45 ,  H01L29/735 ,  H01L27/06 ,  H01L21/84

    CPC分类号： H01L21/8249 ,  H01L21/244 ,  H01L21/84 ,  H01L27/0623 ,  H01L29/1008 ,  H01L29/456 ,  H01L29/6625 ,  H01L29/66545 ,  H01L29/735

    摘要： In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. A dummy gate is formed on the wafer, wherein the dummy gate is present over a portion of the wafer that serves as a base of the bipolar transistor. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer surrounding the dummy gate. The dummy gate is removed selective to the dielectric filler layer, thereby exposing the base. The base is recessed. The base is re-grown from an epitaxial material selected from the group consisting of: SiGe, Ge, and a III-V material. Contacts are formed to the base. Techniques for co-fabricating a bipolar transistor and CMOS FET devices are also provided.

    摘要翻译： 一方面，在晶片上制造双极晶体管器件的方法包括以下步骤。 在晶片上形成虚拟栅极，其中伪栅极存在于作为双极晶体管的基极的晶片的一部分上。 晶圆被掺杂以在虚拟栅极的两侧上形成发射极和集电极区域。 介电填料层沉积在围绕虚拟栅极的晶片上。 对绝缘填料层选择性地去除伪栅极，从而露出基底。 基座凹进。 碱从由SiGe，Ge和III-V材料组成的组中选择的外延材料再生长。 触点形成在基座上。 还提供了用于共同制造双极晶体管和CMOS FET器件的技术。

    Semiconductor device having self-aligned gate contacts
    27.
    发明授权
    Semiconductor device having self-aligned gate contacts 有权
    具有自对准栅接触的半导体器件

    公开(公告)号：US09484205B2

    公开(公告)日：2016-11-01

    申请号：US14585381

    申请日：2014-12-30

    申请人： International Business Machines Corporation

    发明人： Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn

    IPC分类号： H01L21/28 ,  H01L21/283 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

    CPC分类号： H01L21/283 ,  H01L21/76837 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823475 ,  H01L23/535 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/665

    摘要： A semiconductor device and a method for manufacturing the device. The method includes: depositing a first dielectric layer on a semiconductor device; forming a plurality of first trenches through the first dielectric layer; depositing an insulating fill in the plurality of first trenches; planarizing the plurality of first trenches; forming a first gate contact between the plurality of first trenches; depositing a first contact fill in the first gate contact; planarizing the first gate contact; depositing a second dielectric layer on the device; forming a plurality of second trenches through the first and second dielectric layers; depositing a conductive fill in the plurality of second trenches; planarizing the plurality of second trenches; forming a second gate contact where the second gate contact is in contact with the first gate contact; depositing a second contact fill in the second gate contact; and planarizing the second gate contact.

    摘要翻译： 一种半导体器件及其制造方法。 该方法包括：在半导体器件上沉积第一介电层; 通过所述第一介电层形成多个第一沟槽; 在所述多个第一沟槽中沉积绝缘填料; 平面化多个第一沟槽; 在所述多个第一沟槽之间形成第一栅极接触; 在第一栅极接触中沉积第一接触填充物; 平面化第一栅极接触; 在所述器件上沉积第二介电层; 通过所述第一和第二介电层形成多个第二沟槽; 在所述多个第二沟槽中沉积导电填料; 平面化所述多个第二沟槽; 形成第二栅极触点，其中所述第二栅极触点与所述第一栅极触点接触; 在第二栅极接触中沉积第二接触填料; 并平坦化第二栅极接触。

    Self-aligned pitch split for unidirectional metal wiring
    28.
    发明授权
    Self-aligned pitch split for unidirectional metal wiring 有权
    用于单向金属布线的自对准螺距分割

    公开(公告)号：US09472499B2

    公开(公告)日：2016-10-18

    申请号：US13972178

    申请日：2013-08-21

    申请人： International Business Machines Corporation

    发明人： Josephine B. Chang ,  Michael A. Guillorn ,  Eric A. Joseph ,  Hiroyuki Miyazoe

    IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/48

    CPC分类号： H01L23/528 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76841 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/48 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Self-aligned pitch split techniques for metal wiring involving a hybrid (subtractive patterning/damascene) metallization approach are provided. In one aspect, a method for forming a metal wiring layer on a wafer includes the following steps. A copper layer is formed on the wafer. A patterned hardmask is formed on the copper layer. The copper layer is subtractively patterned using the patterned hardmask to form a plurality of first copper lines. Spacers are formed on opposite sides of the first copper lines. A planarizing dielectric material is deposited onto the wafer, filling spaces between the first copper lines. One or more trenches are etched in the planarizing dielectric material. The trenches are filled with copper to form a plurality of second copper lines that are self-aligned with the first copper lines. An electronic device is also provided.

    摘要翻译： 提供了涉及混合（消减图案/镶嵌）金属化方法的金属布线的自对准间距分割技术。 一方面，在晶片上形成金属配线层的方法包括以下步骤。 在晶片上形成铜层。 在铜层上形成图案化的硬掩模。 使用图案化的硬掩模对铜层进行减法图案化以形成多条第一铜线。 隔板形成在第一铜线的相对侧上。 将平坦化介电材料沉积到晶片上，填充第一铜线之间的空间。 在平坦化介电材料中蚀刻一个或多个沟槽。 沟槽用铜填充以形成与第一铜线自对准的多条第二铜线。 还提供电子设备。

    Multiple VT in III-V FETs
    30.
    发明授权
    Multiple VT in III-V FETs 有权
    III-V FET中的多个VT

    公开(公告)号：US09437613B2

    公开(公告)日：2016-09-06

    申请号：US15057900

    申请日：2016-03-01

    申请人： International Business Machines Corporation

    发明人： Josephine B. Chang ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey W. Sleight

    IPC分类号： H01L27/085 ,  H01L27/092 ,  H01L29/66 ,  H01L29/778 ,  H01L21/335 ,  H01L27/12 ,  H01L29/06 ,  H01L29/205 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10

    CPC分类号： H01L27/1203 ,  H01L21/823412 ,  H01L21/8252 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1029 ,  H01L29/20 ,  H01L29/205 ,  H01L29/41783 ,  H01L29/78696

    摘要： In one aspect, a method of forming a multiple VT device structure includes the steps of: forming an alternating series of channel and barrier layers as a stack having at least one first channel layer, at least one first barrier layer, and at least one second channel layer; defining at least one first and at least one second active area in the stack; selectively removing the at least one first channel/barrier layers from the at least one second active area, such that the at least one first channel layer and the at least one second channel layer are the top-most layers in the stack in the at least one first and the at least one second active areas, respectively, wherein the at least one first barrier layer is configured to confine charge carriers to the at least one first channel layer in the first active area.

    摘要翻译： 一方面，一种形成多个VT器件结构的方法包括以下步骤：形成交替的沟道和阻挡层系列作为具有至少一个第一沟道层，至少一个第一势垒层和至少一个第二栅极层 通道层; 限定所述堆叠中的至少一个第一和至少一个第二有效区域; 选择性地从所述至少一个第二有源区域去除所述至少一个第一沟道/势垒层，使得所述至少一个第一沟道层和所述至少一个第二沟道层至少在所述堆叠中的最顶层 一个第一和至少一个第二有源区，其中至少一个第一势垒层被配置为将电荷载流子限制在第一有源区中的至少一个第一沟道层。