公开(公告)号：US20190067101A1

公开(公告)日：2019-02-28

申请号：US15815055

申请日：2017-11-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Su Chen Fan ,  Jeffrey C. Shearer ,  Robert C. Wong ,  Ruilong Xie

IPC: H01L21/768 ,  H01L21/8238 ,  H01L23/535 ,  H01L29/78 ,  H01L27/092 ,  H01L27/11 ,  H01L29/49

Abstract: Embodiments are directed to a semiconductor device. The semiconductor device includes a first semiconductor fin formed opposite a surface of a first active region of a substrate. The semiconductor device further includes a second semiconductor fin formed opposite a surface of a second active region of the substrate. The semiconductor device further includes a self-aligned buried contact formed over portions of the first active region and the second active region and between the first semiconductor fin and the second semiconductor fin.

公开(公告)号：US20180277432A1

公开(公告)日：2018-09-27

申请号：US15813600

申请日：2017-11-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lawrence A. Clevenger ,  Su Chen Fan ,  Huai Huang ,  Koichi Motoyama ,  Wei Wang ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76882 ,  H01L21/76843 ,  H01L23/53257 ,  H01L23/53266

Abstract: A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches.

公开(公告)号：US09953978B2

公开(公告)日：2018-04-24

申请号：US14981574

申请日：2015-12-28

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Kisik Choi ,  Su Chen Fan ,  Shom Ponoth

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/49 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/28114 ,  H01L21/823842 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

Abstract: A transistor device includes a gate structure positioned above a semiconductor substrate, and spaced-apart sidewall spacers positioned above the substrate and adjacent sidewalls of the gate structure. An internal sidewall surface of each of the spaced-apart sidewall spacers includes an upper sidewall surface portion and a lower sidewall surface portion positioned between the upper sidewall surface portion and a surface of the substrate, wherein a first lateral width between first upper ends of the upper sidewall surface portions is greater than a second lateral width between second upper ends of the lower sidewall surface portions.

公开(公告)号：US20170018459A1

公开(公告)日：2017-01-19

申请号：US15277732

申请日：2016-09-27

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Su Chen Fan ,  Sukwon Hong ,  William J. Taylor, JR.

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L23/535 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295

Abstract: An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact.

Abstract translation: 互连结构包括在半导体衬底的上表面上的绝缘体堆叠。 绝缘体堆叠包括具有嵌入其中的至少一个半导体器件的第一绝缘体层和插入在第一绝缘体层和第二绝缘体层之间的蚀刻停止层。 至少一个导电局部接触件延伸穿过第二绝缘体层，蚀刻停止层和与第一半导体器件接触的第一绝缘体层中的每一个。 所述互连结构还包括设置在所述蚀刻停止层上并抵靠所述至少一个导电性局部接触的至少一个第一层接触元件。

公开(公告)号：US09536791B2

公开(公告)日：2017-01-03

申请号：US14748424

申请日：2015-06-24

Applicant: International Business Machines Corporation

Inventor： Su Chen Fan ,  Sivananda K. Kanakasabapathy ,  Injo Ok ,  Tenko Yamashita

IPC: H01L21/304 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/283

CPC classification number: H01L27/0922 ,  H01L21/28114 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553

Abstract: A technique for a multiple voltage threshold transistor structure is provided. A narrow channel and long channel are formed on a fin. An epitaxial layer is formed on the fin, and an interlayer dielectric layer is formed on the epitaxial layer. Spacers on the fin define the narrow channel and the long channel. A high-k dielectric material is deposited in the narrow and long channels. A metal layer is deposited on the high-k dielectric material in the narrow and long channels. A height of the high-k dielectric material in the narrow channel is recessed. The metal layer is removed from the narrow and long channels. A work function metal is deposited in the narrow and long channels. A gate conduction metal is deposited to fill the narrow channel and long channel. A capping layer is deposited on the top surface of the structure.

Abstract translation: 提供了一种用于多电压阈值晶体管结构的技术。 窄通道和长通道形成在翅片上。 在翅片上形成外延层，在外延层上形成层间电介质层。 翅片上的垫片定义了窄通道和长通道。 高k电介质材料沉积在窄通道和长沟道中。 在窄沟道和长沟道中的高k电介质材料上沉积金属层。 窄通道中的高k介电材料的高度凹进。 金属层从窄的和长的通道去除。 工作功能金属沉积在窄通道和长通道中。 沉积栅极导电金属以填充窄沟道和长沟道。 覆盖层沉积在结构的顶表面上。

公开(公告)号：US20160365425A1

公开(公告)日：2016-12-15

申请号：US14739662

申请日：2015-06-15

Applicant: International Business Machines Corporation ,  Samsung Electronics Co., Ltd. ,  Globalfoundries Inc.

Inventor： Hsueh-Chung Chen ,  Su Chen Fan ,  Dong Kwon Kim ,  Sean Lian ,  Fee Li Lie ,  Linus Jang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L29/6653 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/3086 ,  H01L21/31116

Abstract: An aspect of the invention includes a freestanding spacer having a sub-lithographic dimension for a sidewall image transfer process. The freestanding spacer comprises: a first spacer layer having a first portion disposed on the semiconductor layer; and a second spacer layer having a first surface disposed on the first portion of the first spacer layer, wherein the first spacer layer has a first dielectric constant and the second spacer layer has a second dielectric constant, the first dielectric constant being greater than the second dielectric constant, and wherein a dimension of each of the first and second spacer layers collectively determine the sub-lithographic lateral dimension of the freestanding spacer.

Abstract translation: 本发明的一个方面包括具有用于侧壁图像转印过程的亚光刻尺寸的独立间隔物。 独立间隔件包括：第一间隔层，其具有设置在半导体层上的第一部分; 以及第二间隔层，其具有设置在第一间隔层的第一部分上的第一表面，其中第一间隔层具有第一介电常数，第二间隔层具有第二介电常数，第一介电常数大于第二间隔层 介电常数，并且其中第一和第二间隔层中的每一个的尺寸共同确定独立间隔物的亚光刻横向尺寸。

公开(公告)号：US20160293493A1

公开(公告)日：2016-10-06

申请号：US14748424

申请日：2015-06-24

Applicant: International Business Machines Corporation

Inventor： Su Chen Fan ,  Sivananda K. Kanakasabapathy ,  Injo Ok ,  Tenko Yamashita

IPC: H01L21/8234 ,  H01L21/283 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L21/28114 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553

Abstract: A technique for a multiple voltage threshold transistor structure is provided. A narrow channel and long channel are formed on a fin. An epitaxial layer is formed on the fin, and an interlayer dielectric layer is formed on the epitaxial layer. Spacers on the fin define the narrow channel and the long channel. A high-k dielectric material is deposited in the narrow and long channels. A metal layer is deposited on the high-k dielectric material in the narrow and long channels. A height of the high-k dielectric material in the narrow channel is recessed. The metal layer is removed from the narrow and long channels. A work function metal is deposited in the narrow and long channels. A gate conduction metal is deposited to fill the narrow channel and long channel. A capping layer is deposited on the top surface of the structure.

Abstract translation: 提供了一种用于多电压阈值晶体管结构的技术。 窄通道和长通道形成在翅片上。 在翅片上形成外延层，在外延层上形成层间电介质层。 翅片上的垫片定义了窄通道和长通道。 高k电介质材料沉积在窄通道和长沟道中。 在窄沟道和长沟道中的高k电介质材料上沉积金属层。 窄通道中的高k介电材料的高度凹进。 金属层从窄的和长的通道去除。 工作功能金属沉积在窄通道和长通道中。 沉积栅极导电金属以填充窄沟道和长沟道。 覆盖层沉积在结构的顶表面上。

公开(公告)号：US09455254B2

公开(公告)日：2016-09-27

申请号：US14536243

申请日：2014-11-07

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Andre Labonte ,  Su Chen Fan ,  Balasubramanian S. Pranatharthi Haran

IPC: H01L21/8234 ,  H01L21/768 ,  H01L27/088 ,  H01L29/45 ,  H01L23/528 ,  H01L29/66 ,  H01L21/311 ,  H01L21/283 ,  H01L29/417

CPC classification number: H01L27/088 ,  H01L21/283 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/528 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/66515 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method disclosed herein includes, among other things, forming a gate cap layer above a recessed final gate structure and above recessed sidewall spacers, forming a recessed trench silicide region that is conductively coupled to the first source/drain region, the recessed trench silicide region having an upper surface that is positioned at a level that is below the recessed upper surface of the sidewall spacers, forming a combined contact opening in at least one layer of material that exposes a conductive portion of the recessed final gate structure and a portion of the trench silicide region, and forming a combined gate and source/drain contact structure in the combined contact opening.

Abstract translation: 本文公开的一种方法包括在凹陷的最终栅极结构上方和在凹陷的侧壁间隔物上方形成栅极盖层，形成导电耦合到第一源极/漏极区域的凹陷沟槽硅化物区域，凹陷沟槽硅化物区域 具有位于所述侧壁间隔物的凹陷的上表面下方的水平面的上表面，在暴露所述凹入的最终栅极结构的导电部分的至少一层材料中形成组合的接触开口， 沟槽硅化物区域，并且在组合的接触开口中形成组合的栅极和源极/漏极接触结构。

公开(公告)号：US09024389B2

公开(公告)日：2015-05-05

申请号：US13732806

申请日：2013-01-02

Applicant: International Business Machines Corporation

Inventor： Su Chen Fan ,  Balasubramanian S. Haran ,  David V. Horak

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/786 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L21/762 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/76283 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/78609

Abstract: After formation of a semiconductor device on a semiconductor-on-insulator (SOI) layer, a first dielectric layer is formed over a recessed top surface of a shallow trench isolation structure. A second dielectric layer that can be etched selective to the first dielectric layer is deposited over the first dielectric layer. A contact via hole for a device component located in or on a top semiconductor layer is formed by an etch. During the etch, the second dielectric layer is removed selective to the first dielectric layer, thereby limiting overetch into the first dielectric layer. Due to the etch selectivity, a sufficient amount of the first dielectric layer is present between the bottom of the contact via hole and a bottom semiconductor layer, thus providing electrical isolation for the ETSOI device from the bottom semiconductor layer.

Abstract translation: 在半导体绝缘体（SOI）层上形成半导体器件之后，在浅沟槽隔离结构的凹入的顶表面上形成第一介电层。 可以对第一介电层进行蚀刻选择性的第二介电层沉积在第一介电层上。 通过蚀刻形成位于顶部半导体层中或上部的器件部件的接触通孔。 在蚀刻期间，第二电介质层被选择性地移除到第一电介质层，从而将过蚀刻限制到第一介电层中。 由于蚀刻选择性，在接触通孔的底部和底部半导体层之间存在足够量的第一介电层，从而为底部半导体层提供ETSOI器件的电隔离。

公开(公告)号：US08957465B2

公开(公告)日：2015-02-17

申请号：US14285852

申请日：2014-05-23

Applicant: Globalfounfries Singapore Pte. Ltd. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Balasubramanian Pranatharthi Haran ,  David V. Horak ,  Su Chen Fan

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/423 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/42376 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

Abstract: Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape.

Abstract translation: 通过在更换的栅极结构中形成电介质盖来减少接触短路的栅极。 实施例包括在衬底上形成替代的栅极结构，所述替换的栅极结构包括具有空腔的ILD，在ILD的顶表面上的第一金属和衬里的空腔，以及在第一金属上填充空腔的第二金属， 平面化第一和第二金属，在第二金属上形成氧化物，去除氧化物，使空腔中的第一和第二金属凹陷，形成凹陷，并用电介质材料填充凹槽。 实施例还包括具有垂直侧壁，梯形形状，T形或Y形的电介质盖。