公开(公告)号：US20230178635A1

公开(公告)日：2023-06-08

申请号：US18074294

申请日：2022-12-02

Applicant: IMEC VZW

Inventor： Aryan Afzalian ,  Julien Ryckaert ,  Naoto Horiguchi ,  Boon Teik Chan

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L21/308 ,  H01L21/322 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L29/785 ,  H01L29/0847 ,  H01L29/1033 ,  H01L21/308 ,  H01L21/322 ,  H01L21/0262

Abstract: A method for forming a FET device is provided, the method including: forming a fin structure; while masking the fin structure from a second side of the fin structure opposite a first side of the fin structure: etching each of first and second fin parts laterally from the first side such that a set of source cavities and a set of drain cavities is formed in first non-channel layers in the first fin part and the second fin part, and subsequently, forming a source body and a drain body, each comprising a respective common body portion along the first side and a set of prongs protruding from the respective common body portion into the source and drain cavities, respectively, and abutting the channel layers; and while masking the fin structure from the first side: etching the third fin part laterally from the second side such that a set of gate cavities extending through the third fin part is formed in second non-channel layers, and subsequently, forming a gate body comprising a common gate body portion along the second side and a set of gate prongs protruding from the common gate body portion into the gate cavities.

公开(公告)号：US11348842B2

公开(公告)日：2022-05-31

申请号：US17074047

申请日：2020-10-19

Applicant: IMEC VZW

Inventor： Eugenio Dentoni Litta ,  Boon Teik Chan ,  Steven Demuynck

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

Abstract: A method for forming a semiconductor device, the method including: providing a substrate with at least one fin or nanowire; forming a dummy gate; providing spacers on the at least one fin or nanowire and the dummy gate; performing a first RMG module wherein high-k material is provided on at least one fin or nanowire, between the spacers; one or more annealing steps; providing a sacrificial plug between the spacers; epitaxially growing a source and drain in the at least one fin or nanowire; removing the sacrificial plug; performing a second RMG module wherein a WFM is deposited between at least part of the spacers such that the WFM is covering the high-k material of the at least one fin or nanowire.

公开(公告)号：US11335597B2

公开(公告)日：2022-05-17

申请号：US16945858

申请日：2020-08-01

Applicant: IMEC VZW

Inventor： Eugenio Dentoni Litta ,  Anshul Gupta ,  Julien Ryckaert ,  Boon Teik Chan

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/8234

Abstract: A method for forming a buried metal line in a substrate includes forming, at a position between a pair of semiconductor structures protruding from the substrate, a metal line trench in the substrate at a level below a base of each semiconductor structure of the pair. Forming the metal line trench includes etching an upper trench portion in the substrate, forming a spacer on sidewall surfaces of the upper trench portion that expose a bottom surface of the upper trench portion, and, while the spacer masks the sidewall surfaces, etching a lower trench portion by etching the substrate via the upper trench portion such that a width of the lower trench portion exceeds a width of the upper trench portion. The method further includes forming the metal line in the metal line trench.

公开(公告)号：US20210305412A1

公开(公告)日：2021-09-30

申请号：US17210110

申请日：2021-03-23

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Changyong Xiao ,  Jie Chen

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L21/762 ,  H01L29/06

Abstract: A method for processing a FinFET device, such as a Forksheet device, comprises providing a substrate, and forming a trench in the substrate. The trench extends along a first direction. The method further comprises filling the trench with a filling material, and partially recessing the substrate to form a fin structure. The fin structure comprises the filled trench, a first section of the substrate at a first side of the filled trench and a second section of the substrate at a second side of the filled trench, and forming a gate structure on and around the fin structure.

公开(公告)号：US11107812B2

公开(公告)日：2021-08-31

申请号：US16696935

申请日：2019-11-26

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Zheng Tao ,  Steven Demuynck

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L27/092 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: The disclosed technology relates to a method of forming a stacked semiconductor device. One aspect includes fin structures formed by upper and lower channel layers which are separated by an intermediate layer. After preliminary fun cuts are formed in the fin structure, a sacrificial spacer is formed that covers end surfaces of an upper channel layer portion. Final fin cuts are formed in the fin structure where the lower channel layer is etched which defines a lower channel layer portion. Lower source/drain regions are formed on end surfaces of the lower channel layer portion. The sacrificial spacer shields the end surfaces of the upper channel layer portion allowing for selective deposition of material for the lower source/drain regions.

公开(公告)号：US20210020516A1

公开(公告)日：2021-01-21

申请号：US16931230

申请日：2020-07-16

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Yong Kong Siew ,  Juergen Boemmels

IPC: H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/027

Abstract: In one aspect, a method can include forming, by self-aligned multiple patterning, a first pattern of regularly spaced mandrels on a layer to be patterned; forming hard mask spacers on sidewalls of the mandrels, thereby forming a second pattern formed of assemblies comprising a mandrel and hard mask spacers on sidewalls thereof; and etching the second pattern in the layer to be patterned.

公开(公告)号：US10782607B2

公开(公告)日：2020-09-22

申请号：US16123058

申请日：2018-09-06

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Boon Teik Chan ,  Kim Vu Luong ,  Vicky Philipsen ,  Efrain Altamirano Sanchez ,  Kevin Vandersmissen

IPC: G03F1/24 ,  G03F1/22 ,  G03F1/52 ,  G03F1/54 ,  G03F1/48 ,  G03F1/80 ,  G03F7/20 ,  H01L21/768 ,  G03F1/58 ,  B82Y40/00

Abstract: An example method for making a reticle includes providing an assembly. The assembly includes an extreme ultraviolet mirror and a cavity overlaying at least a bottom part of the extreme ultraviolet mirror. The method also includes at least partially filling the cavity with an extreme ultraviolet absorbing structure that includes a metallic material that includes an element selected from Ni, Co, Sb, Ag, In, and Sn, by forming the extreme ultraviolet absorbing structure selectively in the cavity.

公开(公告)号：US10153341B2

公开(公告)日：2018-12-11

申请号：US15822275

申请日：2017-11-27

Applicant: IMEC VZW

Inventor： Zheng Tao ,  Boon Teik Chan ,  Soon Aik Chew

IPC: H01L29/06 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L21/02 ,  B82Y10/00

Abstract: A method of forming a semiconductor device comprising horizontal nanowires is described. An example method involves providing a semiconductor structure comprising at least one fin, where the fin includes an alternating stack of layers of sacrificial material and nanowire material, and where the semiconductor structure includes a dummy gate partly covering the stack of layers. The method further involves at least partly removing the sacrificial material, in between the layers of nanowire material, next to the dummy gate thereby forming a void. Still further, the method involves providing spacer material within the void thereby forming an internal spacer. Yet still further the method involves removing the dummy gate, and selectively removing the sacrificial material in that part of the fin which was covered by the dummy gate, thereby releasing the nanowires. The internal spacer is provided before removing the dummy gate and the sacrificial material to release the nanowires.

公开(公告)号：US20180240699A1

公开(公告)日：2018-08-23

申请号：US15903909

申请日：2018-02-23

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Ming Mao ,  Peter De Schepper ,  Michael Kocsis

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/033 ,  H01L21/027 ,  H01L23/522 ,  H01L29/06

CPC classification number: H01L21/76802 ,  H01L21/0274 ,  H01L21/033 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/5226 ,  H01L29/0649

Abstract: An example embodiment may include a method for blocking one or more portions of one or more trenches during manufacture of a semiconductor structure. The method may include (i) providing a substrate comprising one or more trenches, and a dielectric material under the one or more trenches, (ii) providing a first overlayer on the substrate, thereby filling the one or more trenches, the first overlayer having a planar top surface, a top portion of the first overlayer, comprising the top surface, being etchable selectively with respect to a condensed photo-condensable metal oxide, (iii) covering a first area of the top surface, situated directly above the one or more portions and corresponding thereto, with a block pattern of the condensed photo-condensable metal oxide, thereby leaving a second area of the top surface, having at least another portion of at least one of the trenches thereunder, uncovered.

公开(公告)号：US20170242335A1

公开(公告)日：2017-08-24

申请号：US15433397

申请日：2017-02-15

Applicant: IMEC VZW ,  KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D

Inventor： Boon Teik Chan ,  Arjun Singh ,  Safak Sayan

IPC: G03F7/00 ,  H01L21/033

CPC classification number: G03F7/0002 ,  H01L21/0271 ,  H01L21/0337

Abstract: The present disclosure relates to a patterned structure, the structure comprising: i) a substrate, ii) a first layer on top of the substrate, comprising a filler material and a guiding material, wherein at least a top surface of the first layer comprises one or more zones of filler material and one or more zones of guiding material, and iii) a second layer on top of the first layer comprising a pattern of a first material, the pattern being either aligned or anti-aligned with the underlying one or more zones of guiding material; wherein the first material comprises a metal or a ceramic material and wherein the guiding material and the filler material either both comprise or both do not comprise the metal or ceramic material.