公开(公告)号：US20190035909A1

公开(公告)日：2019-01-31

申请号：US16050163

申请日：2018-07-31

Applicant: Infineon Technologies AG

Inventor： Gerhard Schmidt ,  Johannes Baumgartl ,  Matthias Kuenle ,  Erwin Lercher ,  Daniel Schloegl

IPC: H01L29/66 ,  H01L21/02 ,  C30B15/00 ,  C30B15/20

Abstract: A method for forming a power semiconductor device is provided. The method includes: providing a semiconductor wafer grown by a Czochralski process and having a first side; forming an n-type substrate doping layer in the semiconductor wafer at the first side, the substrate doping layer having a doping concentration of at least 1017/cm3; and forming an epitaxy layer on the first side of the semiconductor wafer after forming the n-type substrate doping layer.

公开(公告)号：US09859395B2

公开(公告)日：2018-01-02

申请号：US14502882

申请日：2014-09-30

Applicant: Infineon Technologies AG

Inventor： Gerhard Schmidt ,  Josef-Georg Bauer ,  Carsten Schaeffer ,  Oliver Humbel ,  Angelika Koprowski ,  Sirinpa Monayakul

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/40 ,  H01L29/861 ,  H01L29/739 ,  H01L29/78 ,  H01L23/31 ,  H01L21/283 ,  H01L29/47 ,  H01L29/06

CPC classification number: H01L29/66143 ,  H01L21/02115 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/283 ,  H01L23/3171 ,  H01L23/3192 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/408 ,  H01L29/47 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.

公开(公告)号：US09312338B2

公开(公告)日：2016-04-12

申请号：US14318921

申请日：2014-06-30

Applicant: Infineon Technologies AG

Inventor： Gerhard Schmidt

IPC: H01L29/00 ,  H01L29/167 ,  H01L21/265 ,  H01L29/10 ,  H01L21/324 ,  H01L21/225

CPC classification number: H01L29/167 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0692 ,  H01L29/0804 ,  H01L29/0834 ,  H01L29/1004 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/8611

Abstract: A semiconductor device includes a single crystalline semiconductor body with a first surface and a second surface parallel to the first surface. The semiconductor body contains chalcogen atoms and a background doping of pnictogen and/or hydrogen atoms. A concentration of the chalcogen atoms is at least 1E12 cm−3. A ratio of the chalcogen atoms to the atoms of the background doping is in a range from 1:9 to 9:1.

Abstract translation: 半导体器件包括具有平行于第一表面的第一表面和第二表面的单晶半导体本体。 半导体主体含有硫属原子和底色和/或氢原子的背景掺杂。 硫属原子的浓度为至少1E12cm-3。 硫属原子与背景掺杂原子的比例在1:9至9:1的范围内。

公开(公告)号：US09287383B2

公开(公告)日：2016-03-15

申请号：US14736420

申请日：2015-06-11

Applicant: Infineon Technologies AG

Inventor： Gerhard Schmidt

IPC: H01L21/22 ,  H01L31/102 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L29/861 ,  H01L29/06 ,  H01L29/739 ,  H01L21/266 ,  H01L21/765 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/66681 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/765 ,  H01L29/0611 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/861

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate having first and second sides, laterally spaced semiconductor devices integrated into the semiconductor substrate, and a drift region of a first conductivity type. Trenches are formed in the semiconductor substrate at the first side of the semiconductor substrate between laterally adjacent semiconductor devices, each of the trenches having two sidewalls and a bottom. First doping zones of a second conductivity type are formed in the semiconductor substrate at least along the sidewalls of the trenches. The first doping zones form pn-junctions with the drift region. Second doping zones of the first conductivity type are formed in the semiconductor substrate at least along a part of the bottom of the trenches. The second doping zones adjoin the drift region. The semiconductor substrate is cut along the second doping zones in the trenches to separate the semiconductor devices.

Abstract translation: 一种制造半导体器件的方法包括提供具有第一和第二侧面的半导体衬底，集成到半导体衬底中的横向间隔开的半导体器件以及第一导电类型的漂移区域。 在半导体衬底的半导体衬底的横向相邻半导体器件之间的半导体衬底中形成沟槽，每个沟槽具有两个侧壁和底部。 至少沿着沟槽的侧壁在半导体衬底中形成第二导电类型的第一掺杂区。 第一掺杂区与漂移区形成pn结。 至少沿着沟槽的底部的一部分，在半导体衬底中形成第一导电类型的第二掺杂区。 第二掺杂区毗邻漂移区。 沿着沟槽中的第二掺杂区切割半导体衬底以分离半导体器件。

公开(公告)号：US09287165B2

公开(公告)日：2016-03-15

申请号：US13927923

申请日：2013-06-26

Applicant: Infineon Technologies AG

Inventor： Gerhard Schmidt ,  Matthias Müller ,  Francisco Javier Santos Rodriguez ,  Daniel Schlögl

IPC: H01L21/76 ,  H01L21/768 ,  H01L29/06

CPC classification number: H01L21/76841 ,  H01L29/0615 ,  H01L29/0619

Abstract: A power semiconductor device includes a semiconductor body, having an active zone and a high voltage peripheral zone laterally adjacent to each other, the high voltage peripheral zone laterally surrounding the active zone. The device further includes a metallization layer on a front surface of the semiconductor body and connected to the active zone, a first barrier layer, comprising a high-melting metal or a high-melting alloy, between the active zone and the metallization layer, and a second barrier layer covering at least a part of the peripheral zone, the second barrier layer comprising an amorphous semi-isolating material. The first barrier layer and the second barrier layer partially overlap and form an overlap zone. The overlap zone extends over an entire circumference of the active zone. A method for producing such a power semiconductor device is also provided.

Abstract translation: 功率半导体器件包括具有横向相邻的有源区和高电压周边区的半导体本体，所述高电压周边区横向围绕有源区。 该器件还包括在半导体主体的前表面上并连接到有源区的金属化层，在活性区和金属化层之间包含高熔点金属或高熔点合金的第一阻挡层，以及 覆盖所述周边区域的至少一部分的第二阻挡层，所述第二阻挡层包括非晶半隔离材料。 第一阻挡层和第二阻挡层部分地重叠并形成重叠区域。 重叠区域在活动区域​​的整个圆周上延伸。 还提供了一种用于制造这种功率半导体器件的方法。

公开(公告)号：US09281360B1

公开(公告)日：2016-03-08

申请号：US14457491

申请日：2014-08-12

Applicant: Infineon Technologies AG

Inventor： Karin Buchholz ,  Matteo Dainese ,  Elmar Falck ,  Hans-Joachim Schulze ,  Gerhard Schmidt ,  Frank Umbach

IPC: H01L29/02 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/404 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8611 ,  H01L29/872

Abstract: A semiconductor device has a semiconductor body including opposing bottom and top sides, a surface surrounding the semiconductor body, an active semiconductor region formed in the semiconductor body, an edge region surrounding the active semiconductor region, a first semiconductor zone of a first conduction type formed in the edge region, an edge termination structure formed in the edge region at the top side, and a shielding structure arranged on that side of the edge termination structure facing away from the bottom side. The shielding structure has a number of N1≧2 first segments and a number of N2≧1 second segments. Each of the first segments is electrically connected to each of the other first segments and to each of the second segments, and each of the second segments has an electric resistivity higher than an electric resistivity of each of the first segments.

Abstract translation: 半导体器件具有半导体本体，该半导体本体包括相对的底部和顶侧，围绕半导体主体的表面，形成在半导体本体中的有源半导体区域，围绕有源半导体区域的边缘区域，形成第一导电类型的第一半导体区域 在边缘区域中，形成在顶侧的边缘区域中的边缘终端结构以及布置在边缘终端结构的背离底侧的那一侧的屏蔽结构。 屏蔽结构具有多个N1≥2个第一段和N 2个≥1个第二段。 每个第一段电连接到每个其它第一段和每个第二段，并且每个第二段具有高于每个第一段的电阻率的电阻率。

公开(公告)号：US20150348824A1

公开(公告)日：2015-12-03

申请号：US14291107

申请日：2014-05-30

Applicant: Infineon Technologies AG

Inventor： Matthias Kuenle ,  Gerhard Schmidt ,  Martin Sporn ,  Markus Kahn ,  Juergen Steinbrenner ,  Ravi Joshi

IPC: H01L21/762 ,  H01L29/40 ,  C23C14/06 ,  C23C14/35 ,  C23C14/58 ,  H01L29/06 ,  C23C14/34

CPC classification number: H01L21/762 ,  C23C14/0605 ,  C23C14/345 ,  C23C14/35 ,  C23C14/5806 ,  H01L21/02527 ,  H01L21/02631 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/408 ,  H01L29/73

Abstract: According to various embodiments, a semiconductor wafer may include: a semiconductor body including an integrated circuit structure; and at least one tetrahedral amorphous carbon layer formed at least one of over or in the integrated circuit structure, the at least one tetrahedral amorphous carbon layer may include a substance amount fraction of sp3-hybridized carbon of larger than approximately 0.4 and a substance amount fraction of hydrogen smaller than approximately 0.1.

Abstract translation: 根据各种实施例，半导体晶片可以包括：包括集成电路结构的半导体本体; 以及至少一个四面体无定形碳层，形成在所述集成电路结构中的至少一个或所述集成电路结构中的至少一个，所述至少一个四面体非晶碳层可以包括大于约0.4的sp3-杂化碳的物质量分数和大于约0.4的物质量分数 的氢小于约0.1。

公开(公告)号：US09082843B2

公开(公告)日：2015-07-14

申请号：US13713867

申请日：2012-12-13

Applicant: Infineon Technologies AG

Inventor： Gerhard Schmidt

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/861 ,  H01L29/06 ,  H01L29/739 ,  H01L21/265 ,  H01L29/20

CPC classification number: H01L29/66681 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/765 ,  H01L29/0611 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/861

Abstract: A semiconductor body has a first side, second side, lateral edge, active area, edge termination between the active area and the lateral edge, and drift region of a first conductivity type. The edge termination includes a step formed in the semiconductor body between the first side and the lateral edge. The step includes a lateral surface extending up to the first side and a bottom surface extending up to the lateral edge. A first doping zone of a second conductivity type is formed in the semiconductor body along the lateral surface of the step and forms a pn-junction with the drift region. A second doping zone of the first conductivity type is formed in the semiconductor body at least along a part of the bottom surface of the step and extends up to the lateral edge, wherein the second doping zone is in contact with the drift region.

Abstract translation: 半导体本体具有第一导电类型的第一侧面，第二侧面，横向边缘，有源区域，有源区域和侧边缘之间的边缘终端以及漂移区域。 边缘终端包括在第一侧面和侧边缘之间形成在半导体本体中的台阶。 该步骤包括一直到第一侧延伸的侧表面和一个延伸到侧边缘的底面。 第二导电类型的第一掺杂区沿着台阶的侧表面形成在半导体本体中，并与漂移区形成pn结。 第一导电类型的第二掺杂区至少沿台阶的底表面的一部分形成在半导体本体中，并且延伸到侧边缘，其中第二掺杂区与漂移区接触。

公开(公告)号：US11804415B2

公开(公告)日：2023-10-31

申请号：US17333107

申请日：2021-05-28

Applicant: Infineon Technologies AG

Inventor： Markus Kahn ,  Oliver Humbel ,  Philipp Sebastian Koch ,  Angelika Koprowski ,  Christian Maier ,  Gerhard Schmidt ,  Juergen Steinbrenner

IPC: H01L29/06 ,  H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  C23C16/34 ,  H01L21/02

CPC classification number: H01L23/3171 ,  C23C16/345 ,  H01L21/0217 ,  H01L21/02271 ,  H01L23/291 ,  H01L23/564 ,  H01L29/0623

Abstract: A semiconductor device includes: a semiconductor body having an active region and an edge termination region between the active region and a side surface of the semiconductor body; a first portion including silicon and nitrogen; a second portion including silicon and nitrogen, the second portion being in direct contact with the first portion; and a front side metallization in contact with the semiconductor body in the active region. The first portion separates the second portion from the semiconductor body. An average silicon content in the first portion is higher than in the second portion. The front side metallization is interposed between the first portion and the semiconductor body in the active region but not in the edge termination region, and/or the first portion and the second portion are both present in the edge termination region but not in the active region.

公开(公告)号：US11075134B2

公开(公告)日：2021-07-27

申请号：US16556642

申请日：2019-08-30

Applicant: Infineon Technologies AG

Inventor： Markus Kahn ,  Oliver Humbel ,  Philipp Sebastian Koch ,  Angelika Koprowski ,  Christian Maier ,  Gerhard Schmidt ,  Juergen Steinbrenner

IPC: H01L23/31 ,  H01L23/29 ,  C23C16/34 ,  H01L23/00 ,  H01L21/02 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor body and a first portion including silicon and nitrogen. The first portion is in direct contact with the semiconductor body. A second portion including silicon and nitrogen is in direct contact with the first portion. The first portion is between the semiconductor body and the second portion. An average silicon content in the first portion is higher than in the second portion.