公开(公告)号：US20200168449A1

公开(公告)日：2020-05-28

申请号：US16677801

申请日：2019-11-08

Applicant: Infineon Technologies AG

Inventor： Sophia Friedler ,  Bernhard Goller ,  Iris Moder ,  Ingo Muri

IPC: H01L21/02 ,  H01L21/465 ,  H01L21/8258

Abstract: A method includes: in a semiconductor wafer including a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a first surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10−2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer.

公开(公告)号：US20170338153A1

公开(公告)日：2017-11-23

申请号：US15596961

申请日：2017-05-16

Applicant: Infineon Technologies AG

Inventor： Johannes Baumgartl ,  Manfred Engelhardt ,  Oliver Hellmund ,  Iris Moder ,  Ingo Muri

IPC: H01L21/78 ,  H01L29/06 ,  H01L21/306 ,  H01L21/304 ,  H01L21/683 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/78 ,  H01L21/02013 ,  H01L21/304 ,  H01L21/3043 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/6835 ,  H01L21/76895 ,  H01L21/82 ,  H01L23/528 ,  H01L29/0657 ,  H01L29/0834 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/861 ,  H01L2221/68327

Abstract: A method for forming a plurality of semiconductor devices includes forming a plurality of trenches extending from a first lateral surface of a semiconductor wafer towards a second lateral surface of the semiconductor wafer. The method further includes filling a portion of the plurality of trenches with filler material. The method further includes thinning the semiconductor wafer from the second lateral surface of the semiconductor wafer to form a thinned semiconductor wafer. The method further includes forming a back side metallization layer structure on a plurality of semiconductor chip regions of the semiconductor wafer after thinning the semiconductor wafer. The method further includes removing a part of the filler material from the plurality of trenches after forming the back side metallization layer structure to obtain the plurality of semiconductor devices.

公开(公告)号：US20230275033A1

公开(公告)日：2023-08-31

申请号：US18109616

申请日：2023-02-14

Applicant: Infineon Technologies AG

Inventor： Thomas Huber ,  Matthias Kuenle ,  Iris Moder ,  Joerg Ortner

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L2223/54426

Abstract: A semiconductor substrate includes a semiconductor base substrate. An alignment structure is formed on a surface of the semiconductor base substrate. An epitaxial layer is deposited on the surface of the semiconductor base substrate. The alignment structure includes an area of the surface of the semiconductor base substrate that is formed as a groove pattern. Grooves of the groove pattern are aligned with a specific crystallographic direction of the semiconductor base substrate. The specific crystallographic direction provides for a slower epitaxial growth rate on such a groove-patterned base substrate surface area compared to epitaxial growth on a surface of the semiconductor base substrate adjacent to the groove-patterned area.

公开(公告)号：US11342433B2

公开(公告)日：2022-05-24

申请号：US16693909

申请日：2019-11-25

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Iris Moder ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze ,  Carsten von Koblinski

IPC: H01L29/49 ,  H01L29/16 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/04 ,  H01L29/45

Abstract: A silicon carbide device includes a silicon carbide substrate having a body region and a source region of a transistor cell. Further, the silicon carbide device includes a titanium carbide gate electrode of the transistor cell.

公开(公告)号：US20180330981A1

公开(公告)日：2018-11-15

申请号：US16032862

申请日：2018-07-11

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Hans-Joachim Schulze ,  Francisco Javier Santos Rodriguez ,  Iris Moder ,  Ingo Muri

IPC: H01L21/762 ,  H01L21/265 ,  H01L21/306

CPC classification number: H01L21/76243 ,  H01L21/02005 ,  H01L21/26533 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/30625 ,  H01L21/324 ,  H01L21/7806

Abstract: According to various embodiments, a method includes: providing a substrate having a first side and a second side opposite the first side; forming a buried layer in and/or over the substrate by implanting a chemical element having a greater electronegativity than the substrate into the first side of the substrate by ion implantation; and thinning the substrate from the second side of the substrate, wherein the buried layer comprises a solid state compound having a greater resistance to the thinning than the substrate and wherein the thinning stops at the buried layer.

公开(公告)号：US20180267408A1

公开(公告)日：2018-09-20

申请号：US15919989

申请日：2018-03-13

Applicant: Infineon Technologies AG

Inventor： Joerg Ortner ,  Iris Moder ,  Ingo Muri

IPC: G03F7/20 ,  G03F1/42

CPC classification number: G03F7/203 ,  G03F1/00 ,  G03F1/42

Abstract: An exposure method includes projecting a reticle pattern into a first exposure field of a photoresist layer, wherein the reticle pattern includes first and second line patterns on opposite edges of the reticle pattern and wherein at least the first line pattern includes an end section through which light flux decreases outwards. The reticle pattern is further projected into a second exposure field of the photoresist layer, wherein a first tapering projection zone of the end section of the first line pattern in the second exposure field overlaps a projection area of the second line pattern in the first exposure field.

公开(公告)号：US10074566B2

公开(公告)日：2018-09-11

申请号：US15596961

申请日：2017-05-16

Applicant: Infineon Technologies AG

Inventor： Johannes Baumgartl ,  Manfred Engelhardt ,  Oliver Hellmund ,  Iris Moder ,  Ingo Muri

IPC: H01L21/301 ,  H01L21/78 ,  H01L21/306 ,  H01L21/311 ,  H01L21/683 ,  H01L21/768 ,  H01L23/528 ,  H01L29/06 ,  H01L21/02 ,  H01L21/304 ,  H01L21/82

CPC classification number: H01L21/78 ,  H01L21/02013 ,  H01L21/304 ,  H01L21/3043 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/6835 ,  H01L21/76895 ,  H01L21/82 ,  H01L23/528 ,  H01L29/0657 ,  H01L29/0834 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/861 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: A method for forming a plurality of semiconductor devices includes forming a plurality of trenches extending from a first lateral surface of a semiconductor wafer towards a second lateral surface of the semiconductor wafer. The method further includes filling a portion of the plurality of trenches with filler material. The method further includes thinning the semiconductor wafer from the second lateral surface of the semiconductor wafer to form a thinned semiconductor wafer. The method further includes forming a back side metallization layer structure on a plurality of semiconductor chip regions of the semiconductor wafer after thinning the semiconductor wafer. The method further includes removing a part of the filler material from the plurality of trenches after forming the back side metallization layer structure to obtain the plurality of semiconductor devices.

公开(公告)号：US20180144982A1

公开(公告)日：2018-05-24

申请号：US15809280

申请日：2017-11-10

Applicant: Infineon Technologies AG

Inventor： Ingo Muri ,  Oliver Hellmund ,  Iris Moder ,  Hans-Joachim Schulze

IPC: H01L21/78 ,  H01L21/265 ,  H01L21/3205 ,  H01L23/14

CPC classification number: H01L21/78 ,  H01L21/265 ,  H01L21/32051 ,  H01L23/14

Abstract: A method is disclosed for use in manufacturing semiconductor dice. The method comprises providing a wafer substrate that comprises dicing areas, providing a first etch stop material outside the dicing areas, and etching the wafer substrate down to the first etch stop material. A semiconductor device chip is also disclosed. The semiconductor device chip comprises a device layer comprising a semiconductor device and a metal support layer supporting the device layer. The metal support layer provides a metal side wall protection of the device layer.

公开(公告)号：US20170133465A1

公开(公告)日：2017-05-11

申请号：US14936279

申请日：2015-11-09

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Frank Pfirsch ,  Hans-Joachim Schulze ,  Ingo Muri ,  Iris Moder ,  Johannes Baumgartl

IPC: H01L29/10 ,  H01L21/265 ,  H01L21/324 ,  H01L27/088 ,  H01L21/306 ,  H01L21/3205 ,  H01L29/78 ,  H01L29/66 ,  H01L21/304

CPC classification number: H01L29/1095 ,  H01L21/265 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/3205 ,  H01L21/324 ,  H01L27/088 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/66477 ,  H01L29/7397 ,  H01L29/78

Abstract: In accordance with a method of forming a semiconductor device, an auxiliary structure is formed at a first surface of a silicon semiconductor body. A semiconductor layer is formed on the semiconductor body at the first surface. Semiconductor device elements are formed at the first surface. The semiconductor body is then removed from a second surface opposite to the first surface at least up to an edge of the auxiliary structure oriented to the second surface.

公开(公告)号：US20170030890A1

公开(公告)日：2017-02-02

申请号：US15221010

申请日：2016-07-27

Applicant: Infineon Technologies AG

Inventor： Gerald Holweg ,  Yonsuang Arnanthigo ,  Jan Berger ,  Guenter Denifl ,  Sylvicley Figueira Da Silva ,  Iris Moder ,  Thomas Ostermann ,  Alexander Oswatitsch ,  Vijaye Kumar Rajaraman ,  Gudrun Stranzl

IPC: G01N33/49 ,  B01D69/02 ,  B01D71/02 ,  B01D61/14

CPC classification number: G01N33/491 ,  B01D61/147 ,  B01D61/18 ,  B01D63/087 ,  B01D69/02 ,  B01D71/02 ,  B01D71/022 ,  B01D71/027 ,  B01D2313/345 ,  B01D2325/02 ,  B01D2325/26

Abstract: A microfiltration device comprises a substrate having a first surface and a second surface opposite to the first surface. The substrate includes a cavity between the first surface and the second surface. The substrate further includes a microfilter including a frame part in contact with the substrate and a filter part abutting the cavity. The microfilter comprises in both the frame part and the filter part a semiconducting or conducting material.

Abstract translation: 微滤装置包括具有第一表面和与第一表面相对的第二表面的基底。 衬底包括在第一表面和第二表面之间的空腔。 该基板还包括一个微型过滤器，它包括一个与该基板接触的框架部分和一个邻接腔体的过滤器部件。 微型过滤器在框架部分和过滤器部分中均包括半导体或导电材料。