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    Structural optimization of contact geometry for high performance connector
    21.
    发明授权
    Structural optimization of contact geometry for high performance connector 有权

    公开(公告)号：US11233348B2

    公开(公告)日：2022-01-25

    申请号：US16857833

    申请日：2020-04-24

    Applicant: Intel Corporation

    Inventor： Se-Jung Moon ,  Chien-Ping Kao ,  Gaudencio Hernandez Sosa ,  Beom-Taek Lee

    IPC: H01R12/73 ,  H01R12/57 ,  H01R12/70

    Abstract: A connector includes a connector housing forming a receptacle configured to receive an add-in card. The connector further includes a first connector pin configured to electrically couple to the add-in card responsive to the add-in card being inserted into the receptacle. The first connector pin extends from the connector housing to contact a first solder pad disposed on a printed circuit board (PCB). The connector further includes a second connector pin configured to electrically couple to the add-in card responsive to the add-in card being inserted into the receptacle. The second connector pin extends from the connector housing to contact a second solder pad disposed on the PCB. The first connector pin is oriented toward the second connector pin to couple to the PCB in a toe-routing configuration and the second connector pin is oriented away from the first connector pin to couple to the PCB in the toe-routing configuration.

    SYSTEM, APPARATUS AND METHOD FOR INTERCONNECTING CIRCUIT BOARDS
    25.
    发明申请
    SYSTEM, APPARATUS AND METHOD FOR INTERCONNECTING CIRCUIT BOARDS 审中-公开
    用于互连电路板的系统，装置和方法

    公开(公告)号：US20170079140A1

    公开(公告)日：2017-03-16

    申请号：US14851083

    申请日：2015-09-11

    Applicant: Intel Corporation

    Inventor： Raul Enriquez Shibayama ,  Kai Xiao ,  Nicte A. Zavala Castro ,  Beom-Taek Lee

    IPC: H05K1/14 ,  H05K1/11 ,  H05K1/02 ,  H05K1/18

    CPC classification number: H05K1/144 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/181 ,  H05K1/184 ,  H05K3/368 ,  H05K2201/041 ,  H05K2201/09545 ,  H05K2201/10159 ,  H05K2201/10303 ,  H05K2201/10734

    Abstract: In one embodiment, first and second circuit boards may be coupled together. The first circuit board may include a first trace to electrically couple a first integrated circuit to a first via of the first circuit board. In turn, the second circuit board may include a second trace to electrically couple a first contact of a first memory socket adapted to the first circuit board and a first contact of a second memory socket adapted to the first circuit board. This second trace, when the circuit boards are coupled together, is to electrically couple to a first via of the second circuit board, to enable the first via of the second board to electrically couple to the first via of the first circuit board. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，第一和第二电路板可以耦合在一起。 第一电路板可以包括将第一集成电路电耦合到第一电路板的第一通孔的第一迹线。 反过来，第二电路板可以包括第二迹线，用于电耦合适于第一电路板的第一存储器插座的第一触点和适于第一电路板的第二存储器插槽的第一触点。 当电路板耦合在一起时，该第二迹线将电耦合到第二电路板的第一通孔，以使得第二板的第一通孔能够电耦合到第一电路板的第一通孔。 描述和要求保护其他实施例。

    COMPACT VIA STRUCTURES AND METHOD OF MAKING SAME
    26.
    发明申请
    COMPACT VIA STRUCTURES AND METHOD OF MAKING SAME 审中-公开
    紧凑的结构和制作方法

    公开(公告)号：US20160378215A1

    公开(公告)日：2016-12-29

    申请号：US14752642

    申请日：2015-06-26

    Applicant: INTEL CORPORATION

    Inventor： Kai Xiao ,  Raul Enriquez Shibayama ,  Gong Ouyang ,  Jose Diego Guillen Gonzalez ,  Beom-Taek Lee

    IPC: G06F3/041 ,  H01P3/08

    CPC classification number: H01P3/08 ,  H01P5/028 ,  H05K1/0251 ,  H05K1/116 ,  H05K3/403 ,  H05K3/429 ,  H05K2201/09645 ,  H05K2201/09854

    Abstract: Techniques and mechanisms to provide a compact arrangement of vias extending through at least a portion of a printed circuit board (PCB) or other substrate. In an embodiment, the substrate includes a dielectric material and a sidewall structure forming a hole region that extends at least partially through the dielectric material. The hole region adjoins each of a first via and a second via, and is also located between the first via and second via. In another embodiment, the first via is coupled to exchange a first signal of a differential signal pair, and the second via is coupled to exchange a second signal of the same differential signal pair.

    Abstract translation: 提供延伸穿过印刷电路板（PCB）或其它基板的至少一部分的通孔的紧凑布置的技术和机构。 在一个实施例中，衬底包括电介质材料和形成至少部分延伸穿过电介质材料的孔区的侧壁结构。 孔区域邻接第一通孔和第二通孔中的每一个，并且还位于第一通孔和第二通孔之间。 在另一个实施例中，第一通孔被耦合以交换差分信号对的第一信号，并且第二通孔被耦合以交换相同差分信号对的第二信号。

    INDUCTORS FOR CIRCUIT BOARD THROUGH HOLE STRUCTURES
    27.
    发明申请
    INDUCTORS FOR CIRCUIT BOARD THROUGH HOLE STRUCTURES 有权
    电路板通过孔结构的电感器

    公开(公告)号：US20160276092A1

    公开(公告)日：2016-09-22

    申请号：US14678714

    申请日：2015-04-03

    Applicant: Intel Corporation

    Inventor： Zhichao Zhang ,  Gong Ouyang ,  Kai Xiao ,  Kemal Aygun ,  Beom-Taek Lee

    IPC: H01F27/28 ,  H05K1/18 ,  H05K1/02 ,  H05K1/11

    CPC classification number: H05K1/0237 ,  H01F17/0013 ,  H01F2017/002 ,  H05K1/0233 ,  H05K1/116 ,  H05K1/165

    Abstract: Systems, apparatuses, and methods may include a circuit board having a plated through hole with a via portion and a stub portion and a self-coupled inductor electrically coupled to the via portion of the plated through hole. The self-coupled inductor may include a first inductor mutually coupled to a second inductor in series to reduce a capacitive effect of the stub portion of the plated through hole.

    Abstract translation: 系统，装置和方法可以包括具有电镀通孔的电路板，其具有通孔部分和短截线部分，以及电耦合到电镀通孔的通孔部分的自耦合电感器。 自耦合电感器可以包括串联耦合到第二电感器的第一电感器，以减小电镀通孔的短截线部分的电容效应。

    CIRCUIT COMPONENT BRIDGE DEVICE
    29.
    发明申请
    CIRCUIT COMPONENT BRIDGE DEVICE 有权
    电路元件桥接器件

    公开(公告)号：US20150223336A1

    公开(公告)日：2015-08-06

    申请号：US14169423

    申请日：2014-01-31

    Applicant: INTEL CORPORATION

    Inventor： Beom-Taek Lee ,  Raul Enriquez-Shibayama ,  Carolina Garcia Robles

    IPC: H05K1/18 ,  H05K1/11 ,  H05K3/40 ,  H05K1/02

    CPC classification number: H05K1/18 ,  H05K1/0216 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/115 ,  H05K1/144 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4038 ,  H05K2201/10734 ,  H05K2203/1461 ,  Y10T29/49165

    Abstract: A bridge device is described herein. The bridge device may include a first via of a bridge device, the first via of the bridge device having a short via stub or no via stub, the first via of the bridge device to be communicatively coupled to a first via of a printed circuit board (PCB). The bridge device may include a second via of the bridge device, the second via of the bridge device having a short via stub or no via stub, the second via of the bridge device to be communicatively coupled to a second via of the PCB. A trace of the bridge device may communicatively couple the first via of the bridge device to the second via of the bridge device.

    Abstract translation: 这里描述了桥接设备。 桥接器件可以包括桥接器件的第一通孔，桥接器件的第一通路具有短通孔短路或非通路短路，桥接器件的第一通孔可通信地耦合到印刷电路板的第一通孔 （PCB）。 桥接器件可以包括桥接器件的第二通孔，桥接器件的第二通孔具有短通孔短截线或没有通孔短路，桥接器件的第二通孔可通信地耦合到PCB的第二通孔。 桥接器件的迹线可以将桥接器件的第一通路通信地耦合到桥接器件的第二通孔。

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