公开(公告)号：US20240219644A1

公开(公告)日：2024-07-04

申请号：US18090260

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Benjamin Duong ,  Hiroki Tanaka ,  Brandon Marin ,  Jeremy Ecton ,  Gang Duan ,  Srinivas Pietambaram ,  Hari Mahalingam

IPC: G02B6/35 ,  G02B6/42 ,  H01L23/498

CPC classification number: G02B6/35 ,  G02B6/4274 ,  H01L23/49816

Abstract: An integrated circuit (IC) module includes a photonic IC, an electrical IC, and a switchable waveguide device that, using a signal from the electrical IC, controls optical signals to or from the photonic IC. The switchable waveguide device may be formed by coupling metallization structures on both sides of, and either level with or below, a nonlinear optical material. The metallization structures may be in the photonic or electrical IC. The nonlinear optical material may be above the electrical IC in the photonic IC or on a glass substrate. The photonic and electrical ICs may be hybrid bonded or soldered together. The IC module may be coupled to a system substrate.

公开(公告)号：US20240194657A1

公开(公告)日：2024-06-13

申请号：US18080152

申请日：2022-12-13

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Brandon Marin ,  Jeremy Ecton ,  Gang Duan ,  Srinivas Pietambaram

IPC: H01L25/16 ,  G02B6/42 ,  H01L21/56 ,  H01L23/00 ,  H01L23/433

CPC classification number: H01L25/167 ,  G02B6/4239 ,  G02B6/4245 ,  G02B6/4257 ,  G02B6/4269 ,  H01L21/565 ,  H01L23/4334 ,  H01L24/08 ,  H01L24/80 ,  G02B6/426 ,  H01L24/16 ,  H01L2224/08121 ,  H01L2224/08148 ,  H01L2224/16225 ,  H01L2224/80895 ,  H01L2924/1431 ,  H01L2924/182

Abstract: Apparatuses, systems, assemblies, and techniques related to integrating photonics integrated circuit devices and electronic integrated circuit devices into an assembly or module are described. An integrated module includes a photonics integrated circuit device within an opening of a glass core substrate and an electronic integrated circuit device direct bonded to the photonics integrated circuit device. An optical waveguide is within or on the glass core substrate and has a terminal end edge coupled to the photonics integrated circuit device within the opening.

公开(公告)号：US20240113075A1

公开(公告)日：2024-04-04

申请号：US17956363

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon Marin ,  Srinivas Pietambaram ,  Gang Duan ,  Suddhasattwa Nad

IPC: H01L25/065 ,  H01L21/52 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L21/52 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389

Abstract: Multi-die packages including a glass substrate within a space between adjacent IC dies. Two or more IC die may be placed within recesses formed in a glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. Organic package dielectric material may then be built up on both sides of the IC dies and glass substrate. Metallization features formed within package dielectric material built up on a first side of the IC die may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects. Metallization features formed within package dielectric material built up on a second side of the first and second IC dies may electrically interconnect the first IC die to the second IC die.

公开(公告)号：US20220413233A1

公开(公告)日：2022-12-29

申请号：US17357788

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Hiroki Tanaka ,  Kristof Darmawikarta ,  Brandon Marin ,  Robert May ,  Sri Ranga Sai Boyapati

IPC: G02B6/42

Abstract: An optical package comprising an optical die that is electrically coupled to a package substrate, and an optical interconnect adjacent the optical die. The optical interconnect comprises a first polarizing filter adjacent to a first lens, a second polarizing filter adjacent to a second lens; and a film comprising a magnetic material between the first polarizing filter and the second polarizing filter. The second polarizing filter is rotated with respect to the first polarizing filter and the magnetic material is to rotate a polarization vector of light incoming to the optical interconnect. An optical fiber interface port is immediately adjacent to the first lens. The second lens is immediately adjacent to an optical interface of the optical die.

公开(公告)号：US12033930B2

公开(公告)日：2024-07-09

申请号：US17033392

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Jieying Kong ,  Yiyang Zhou ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Hongxia Feng ,  Tarek Ibrahim ,  Brandon Marin ,  Zhiguo Qian ,  Sarah Blythe ,  Bohan Shan ,  Jason Steill ,  Sri Chaitra Jyotsna Chavali ,  Leonel Arana ,  Dingying Xu ,  Marcel Wall

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/485 ,  H01L23/49827

Abstract: An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.

公开(公告)号：US20240194608A1

公开(公告)日：2024-06-13

申请号：US18080612

申请日：2022-12-13

Applicant: Intel Corporation

Inventor： Gang Duan ,  Rahul Manepalli ,  Srinivas Pietambaram ,  Brandon Marin ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5384 ,  H01L2221/68359

Abstract: An integrated circuit (IC) package comprises a first IC die having first metallization features, a second IC die having second metallization features, and a third IC die having third metallization features. A glass layer is between the third IC die and both of the first IC die and the second IC die. A plurality of first through vias extend through the glass layer, coupling the third metallization features with first ones of the first metallization features and with first ones of the second metallization features. A plurality of second through vias extend through the glass layer. A dielectric material is around the third die and a package metallization is within the dielectric material. The package metallization is coupled to at least one of the first, second, or third IC die, and terminating at a plurality of package interconnect interfaces.

公开(公告)号：US11804420B2

公开(公告)日：2023-10-31

申请号：US16020122

申请日：2018-06-27

Applicant: INTEL CORPORATION

Inventor： Brandon Marin ,  Whitney Bryks

IPC: H01L23/492 ,  H01L23/532 ,  H01L23/498 ,  H01L21/02

CPC classification number: H01L23/4922 ,  H01L23/4924 ,  H01L23/49822 ,  H01L23/49894 ,  H01L21/02112 ,  H01L23/5329

Abstract: A package substrate may include a build-up layer. The build-up layer may include a dielectric material and one or more microspheres. The one or more microspheres may include a magnetic core that includes a first material that is a first oxidation-resistant material. Further, the one or more microspheres may include a shell to encapsulate the core, and the shell may include a second material that is a second oxidation-resistant material. The package substrate may further include a metal layer coupled with the build-up layer.

公开(公告)号：US20230090449A1

公开(公告)日：2023-03-23

申请号：US17448693

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Gang Duan ,  Jeremy Ecton ,  Brandon Marin ,  Ravindranath Mahajan

IPC: H01L23/00

Abstract: Methods, systems, apparatus, and articles of manufacture to produce nano-roughened integrated circuit packages are disclosed. An example integrated circuit (IC) package includes a substrate, a semiconductor die, and a metal interconnect to electrically couple the semiconductor die to the substrate, the metal interconnect including a nano-roughened surface.

公开(公告)号：US20220404551A1

公开(公告)日：2022-12-22

申请号：US17349305

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Pooya Tadayon ,  Zhichao Zhang ,  Brandon Marin ,  Tarek Ibrahim ,  Kemal Aygun ,  Stephen Smith

IPC: G02B6/12 ,  G02B6/122

Abstract: Integrated circuit packages may be formed having at least one optical via extending from a first surface of a package substrate to an opposing second surface of the package substrate. The at least one optical via creates an optical link between the opposing surfaces of the package substrate that enables the fabrication of a dual-sided optical multiple chip package, wherein integrated circuit devices can be attached to both surfaces of the package substrate for increased package density.

公开(公告)号：US20220352076A1

公开(公告)日：2022-11-03

申请号：US17243784

申请日：2021-04-29

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon Marin ,  Srinivas Pietambaram ,  Suddhasattwa Nad

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00

Abstract: An electronic substrate may be fabricated having at least two glass layers separated by an etch stop layer, wherein a bridge is embedded within one of the glass layers. The depth of a cavity formed for embedding the bridge is control by the thickness of the glass layer rather than by controlling the etching process used to form the cavity, which allows for greater precision in the fabrication of the electronic substrate. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate, such that the bridge provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board.