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    RECONFIGURABLE CLOCKING ARCHITECTURE
    21.
    发明申请
    RECONFIGURABLE CLOCKING ARCHITECTURE 有权

    公开(公告)号：US20170243627A1

    公开(公告)日：2017-08-24

    申请号：US15047427

    申请日：2016-02-18

    Applicant: Intel Corporation

    Inventor： Mozhgan Mansuri ,  Aaron Martin ,  James A. McCall

    IPC: G11C11/4076 ,  H03K5/14

    CPC classification number: G11C11/4076 ,  G06F1/10 ,  G06F13/4234 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4093 ,  H03K5/14 ,  H03K2005/00052 ,  H04L7/0337

    Abstract: Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.

    Memory device specific self refresh entry and exit
    22.
    发明申请
    Memory device specific self refresh entry and exit 审中-公开
    内存设备特定的自刷新进入和退出

    公开(公告)号：US20160350002A1

    公开(公告)日：2016-12-01

    申请号：US14998058

    申请日：2015-12-26

    Applicant: Intel Corporation

    Inventor： George Vergis ,  Kuljit S. Bains ,  James A. McCall ,  Murugasamy K. Nachimuthu ,  Mohan J. Kumar

    IPC: G06F3/06

    CPC classification number: G06F12/02 ,  G11C5/04 ,  G11C11/40615 ,  G11C11/4074 ,  G11C2211/4067

    Abstract: A system enables memory device specific self-refresh entry and exit commands. When memory devices on a shared control bus (such as all memory devices in a rank) are in self-refresh, a memory controller can issue a device specific command with a self-refresh exit command and a unique memory device identifier to the memory device. The controller sends the command over the shared control bus, and only the selected, identified memory device will exit self-refresh while the other devices will ignore the command and remain in self-refresh. The controller can then execute data access over a shared data bus with the specific memory device while the other memory devices are in self-refresh.

    Abstract translation: 系统启用存储设备特定的自刷新进入和退出命令。 当共享控制总线（诸如等级上的所有存储设备）中的存储设备进行自刷新时，存储器控制器可以向存储器设备发出具有自刷新退出命令和唯一存储器设备标识符的特定于设备的命令 。 控制器通过共享控制总线发送命令，只有选定的已识别的存储设备将退出自刷新，而其他设备将忽略该命令并保持自刷新。 然后，控制器可以通过共享数据总线与特定存储器设备执行数据访问，而其他存储器件处于自刷新状态。

    I/O driver transmit swing control
    23.
    发明授权
    I/O driver transmit swing control 有权
    I / O驱动器发送摆幅控制

    公开(公告)号：US09374004B2

    公开(公告)日：2016-06-21

    申请号：US13931604

    申请日：2013-06-28

    Applicant: Intel Corporation

    Inventor： Christopher P. Mozak ,  Ritesh B. Trivedi ,  James A. McCall ,  Aaron Martin

    IPC: H03K19/0175 ,  H03K19/0185 ,  H02M3/158 ,  G11C29/02 ,  G11C7/10 ,  H04L25/02

    CPC classification number: H02M3/158 ,  G11C7/1057 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C2207/105 ,  H04L25/0276 ,  H04L25/029

    Abstract: A transmission line interface circuit includes a voltage regulator to control a voltage swing of the transmission line interface circuit for signal transmission. The transmission line interface circuit includes complementary driver elements, including a p-type driver element to pull up the transmission line in response to a logic high, and an n-type driver element to pull down the transmission line in response to a logic low. The voltage regulator is coupled between one of the driver elements and a respective voltage reference to reduce a voltage swing of the transmission line interface circuit.

    Abstract translation: 传输线接口电路包括用于控制用于信号传输的传输线接口电路的电压摆幅的电压调节器。 传输线接口电路包括互补驱动器元件，包括响应于逻辑高来上拉传输线的p型驱动器元件，以及响应于逻辑低来拉低传输线的n型驱动器元件。 电压调节器耦合在驱动器元件之一和相应的电压基准之间，以减小传输线接口电路的电压摆幅。

    METHOD AND APPARATUS FOR DYNAMIC MEMORY TERMINATION
    24.
    发明申请
    METHOD AND APPARATUS FOR DYNAMIC MEMORY TERMINATION 有权
    用于动态记忆终止的方法和装置

    公开(公告)号：US20160065212A1

    公开(公告)日：2016-03-03

    申请号：US14838373

    申请日：2015-08-28

    Applicant: Intel Corporation

    Inventor： James A. McCall ,  Kuljit S. Bains

    IPC: H03K19/00 ,  G11C7/10

    CPC classification number: H03K19/0005 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/4074 ,  G11C11/4093

    Abstract: Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.

    Abstract translation: 这里描述了一种用于响应于终止信号电平在存储器的存储器输入 - 输出（I / O）接口之间动态切换一个或多个有限终端阻抗值设置的方法和装置。 该方法包括：为存储器的输入输出（I / O）接口的终端单元设置第一终端阻抗值设置; 当所述存储器未被访问时，将所述第一终端阻抗值设置分配给所述终端单元; 以及响应于终止信号电平从第一终端阻抗值设置切换到第二终端阻抗值设置。

    APPARATUS, METHOD AND SYSTEM FOR PROVIDING TERMINATION FOR MULTIPLE CHIPS OF AN INTEGRATED CIRCUIT PACKAGE
    25.
    发明申请
    APPARATUS, METHOD AND SYSTEM FOR PROVIDING TERMINATION FOR MULTIPLE CHIPS OF AN INTEGRATED CIRCUIT PACKAGE 审中-公开
    用于提供集成电路封装多个引脚的终止的装置，方法和系统

    公开(公告)号：US20150279444A1

    公开(公告)日：2015-10-01

    申请号：US14440068

    申请日：2013-11-22

    Applicant: George VERGIS ,  Kuljit S. BAINS ,  James A. MCCALL ,  Ge CHANG ,  INTEL CORPORATION

    Inventor： George Vergis ,  Kuljit S. Bains ,  James A. McCall ,  Ge Chang

    IPC: G11C11/4074 ,  G11C7/10 ,  G06F13/16 ,  G11C11/408

    CPC classification number: G11C11/4074 ,  G06F3/0604 ,  G06F3/0637 ,  G06F3/0673 ,  G06F13/1663 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1084 ,  G11C7/109 ,  G11C8/06 ,  G11C11/408 ,  Y10T29/41

    Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series

    Abstract translation: 用于为存储器件的多个芯片提供终端的技术和机制。 在一个实施例中，存储器件是集成电路（IC）封装，其包括命令和地址总线以及与其耦合的多个存储器芯片。 在多个存储器芯片中，只有第一存储器芯片可操作以选择性地提供对命令和地址总线的终止。 在多个存储器芯片的各个片上终端控制电路中，仅第一存储器芯片的片上终端控制电路经由任何终端控制信号线耦合到任何输入/输出（I / O）触点 IC封装。 在另一个实施例中，多个存储器芯片彼此串联配置，并且其中第一存储器芯片位于该系列的一端

    Package pin pattern for device-to-device connection
    26.
    发明授权
    Package pin pattern for device-to-device connection 有权

    公开(公告)号：US12073906B2

    公开(公告)日：2024-08-27

    申请号：US17086220

    申请日：2020-10-30

    Applicant: Intel Corporation

    Inventor： Chong J. Zhao ,  James A. McCall ,  Robert J. Friar ,  Yidnekachew S. Mekonnen ,  San K. Chhay

    IPC: H05K7/00 ,  G11C5/06 ,  G11C8/18 ,  H05K5/02

    CPC classification number: G11C5/06 ,  G11C8/18 ,  H05K5/0286

    Abstract: Examples described herein relate to a pattern of pins where the signals assigned to the pins are arranged in a manner to reduce cross-talk. In some examples, a socket substrate includes a first group of pins that includes a first group of data (DQ) pins separated by at least two Voltage Source Supply (VSS) pins from a second group of DQ pins and a third group of DQ pins separated by at least two VSS pins from a fourth group of DQ pins. In some examples, data strobe signal (DQS) pins are positioned in a column between the first and third groups of DQ pins and the second and fourth groups of DQ pins. In some examples, a second group of pins includes a first group of DQ pins separated by at least two VSS pins from a second group of DQ pins and a third group of DQ pins separated by at least two VSS pins from a fourth group of DQ pins. In some examples, the second group of pins, DQS pins are positioned between the first and third groups of DQ pins and the second and fourth groups of DQ pins.

    Reconfigurable clocking architecture
    29.
    发明授权
    Reconfigurable clocking architecture 有权

    公开(公告)号：US10134463B2

    公开(公告)日：2018-11-20

    申请号：US15727850

    申请日：2017-10-09

    Applicant: Intel Corporation

    Inventor： Mozhgan Mansuri ,  Aaron Martin ,  James A. McCall

    IPC: G11C7/00 ,  G11C11/4076 ,  G06F1/10 ,  G11C7/10 ,  G11C7/22 ,  H03K5/14 ,  H04L7/033 ,  H03K5/00

    Abstract: Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.

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