公开(公告)号：US09431274B2

公开(公告)日：2016-08-30

申请号：US13722886

申请日：2012-12-20

Applicant: Intel Corporation

Inventor： Suriyakala Ramalingam ,  Manish Dubey ,  Hsin-Yu Li ,  Michelle S. Phen ,  Hitesh Arora ,  Nisha Ananthakrishnan ,  Yiqun Bai ,  Yonghao Xiu ,  Rajendra C. Dias

IPC: H01L21/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29

CPC classification number: H01L21/563 ,  H01L23/295 ,  H01L24/09 ,  H01L24/17 ,  H01L24/29 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/29386 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于具有以通常随机分布图案排列的填充颗粒的底部填充层的集成电路（IC）封装的技术和配置。 在一些实施例中，通过对IC封装组件的一个或多个部件上的静电电荷，通过对填料进行表面处理以减少填充剂电荷，可以通过施加电力来抵抗填料颗粒的大致随机分布图案 通过使用相对较低的最大填充剂粒度的底部填充材料和/或通过在相对低的温度下快速固化底部填充层，使底部填充材料的填料颗粒在与重力方向相反的方向上。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09230833B2

公开(公告)日：2016-01-05

申请号：US14638328

申请日：2015-03-04

Applicant: INTEL CORPORATION

Inventor： Manish Dubey ,  Rajendra C. Dias ,  Yonghao Xiu ,  Arjun Krishnan ,  Yiqun Bai ,  Purushotham Kaushik Muthur Srinath

IPC: H01L21/56 ,  H01L23/00

CPC classification number: H01L21/563 ,  H01L23/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particless within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.

Abstract translation: 本说明书的实施例包括在微电子器件上处理底部填充材料之后将微电子器件附着到具有互连结构的微电子衬底的方法，其中，在将微电子器件连接到微电子器件之前，底部填充材料内的填料颗粒可能被排除离开互连结构 器件到微电子结构。 这些方法可以包括在互连结构上引入电荷，并且可以包括将互连结构放置在相对的板之间，并且在将底部填充材料沉积在互连结构上之后在相对的板之间产生偏压。

公开(公告)号：US20220181262A1

公开(公告)日：2022-06-09

申请号：US17677130

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US20210391273A1

公开(公告)日：2021-12-16

申请号：US16902777

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Jinhe Liu ,  Sairam Agraharam ,  Mohit Bhatia ,  Edvin Cetegen

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20210013117A1

公开(公告)日：2021-01-14

申请号：US16504698

申请日：2019-07-08

Applicant: Intel Corporation

Inventor： Peng Li ,  Kelly P. Lofgreen ,  Manish Dubey ,  Bamidele Daniel Falola ,  Ken Hackenberg ,  Shenavia S. Howell ,  Sergio Antonio Chan Arguedas ,  Yongmei Liu ,  Deepak Goyal

IPC: H01L23/34 ,  H01L23/367 ,  H01L23/433 ,  H01L21/48

Abstract: Embodiments may relate to a microelectronic package that includes a lid coupled with a package substrate such that a die is positioned between the lid and the package substrate. The lid may include a heating element that is to heat an area between the lid and the die. Other embodiments may be described or claimed.

公开(公告)号：US10651108B2

公开(公告)日：2020-05-12

申请号：US15197440

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Zhizhong Tang ,  Syadwad Jain ,  Wei Hu ,  Michael A. Schroeder ,  Rajen S. Sidhu ,  Carl L. Deppisch ,  Patrick Nardi ,  Kelly P. Lofgreen ,  Manish Dubey

IPC: H05K5/00 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01L23/42 ,  F28F13/00 ,  F28F21/04 ,  F28F21/02 ,  F28F21/08 ,  F28D21/00

Abstract: Devices and methods disclosed herein can include a conductive foam having pores disposed within the conductive foam. The conductive foam can be compressible between an uncompressed thickness and a compressed thickness. The compressed thickness can be ninety-five percent or less of the uncompressed thickness. In one example, a filler can be disposed in the pores of the conductive foam. The filler can include a first thermal conductivity. The first thermal conductivity can be greater than a thermal conductivity of air.

公开(公告)号：US10206277B2

公开(公告)日：2019-02-12

申请号：US14975162

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Manish Dubey ,  Tatyana N. Andryushchenko ,  Aleksandar Aleksov ,  David W. Staines

IPC: H05K1/00 ,  H05K1/02 ,  A41D1/00 ,  A43B3/00 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/32

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for gradient encapsulant protection of devices in stretchable electronic. For instance, in accordance with one embodiment, there is an apparatus with an electrical device on a stretchable substrate; one or more stretchable electrical interconnects coupled with the electrical device; one or more electrical components electrically coupled with the electrical device via the one or more stretchable electrical interconnects; and a gradient encapsulating material layered over and fully surrounding the electrical device and at least a portion of the one or more stretchable electrical interconnects coupled thereto, in which the gradient encapsulating material has an elastic modulus greater than the stretchable substrate and in which the elastic modulus of the gradient encapsulating material is less than the electrical device. Other related embodiments are disclosed.

公开(公告)号：US09721906B2

公开(公告)日：2017-08-01

申请号：US14841052

申请日：2015-08-31

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Rajendra C. Dias ,  Baris Bicen ,  Digvijay Raorane ,  Bharat P. Penmecha

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/563 ,  H01L23/3142 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32225 ,  H01L2224/83801 ,  H01L2924/1511 ,  H01L2924/1515 ,  H01L2924/3511

Abstract: An electronic package that includes a substrate and a die attached to the substrate. A plurality of supports attached to the substrate adjacent to the die. At least one support in the plurality of supports is positioned adjacent to at least one corner of the die such that the at least one corner of the die is positioned adjacent to the at least one support. Other example forms relate to a method of fabricating an electronic package. The method includes securing a die to a substrate and securing a plurality of supports to the substrate such that at least one support is adjacent to at least one corner of the die.

公开(公告)号：US12176268B2

公开(公告)日：2024-12-24

申请号：US16828405

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Digvijay Raorane ,  Sairam Agraharam ,  Nitin Deshpande ,  Mitul Modi ,  Manish Dubey ,  Edvin Cetegen

IPC: H01L23/48 ,  H01L23/482 ,  H01L23/495 ,  H01L23/538

Abstract: Embodiments disclosed herein include multi-die packages with open cavity bridges. In an example, an electronic apparatus includes a package substrate having alternating metallization layers and dielectric layers. The package substrate includes a first plurality of substrate pads and a second plurality of substrate pads. The package substrate also includes an open cavity between the first plurality of substrate pads and the second plurality of substrate pads, the open cavity having a bottom and sides. The electronic apparatus also includes a bridge die in the open cavity, the bridge die including a first plurality of bridge pads, a second plurality of bridge pads, and conductive traces. An adhesive layer couples the bridge die to the bottom of the open cavity. A gap is laterally between the bridge die and the sides of the open cavity, the gap surrounding the bridge die.

公开(公告)号：US11817390B2

公开(公告)日：2023-11-14

申请号：US18090795

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5381 ,  H01L23/3185 ,  H01L23/367 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.