公开(公告)号：US20160181424A1

公开(公告)日：2016-06-23

申请号：US14909981

申请日：2013-09-26

Applicant: INTEL CORPORATION

Inventor： Rafael RIOS ,  Roza KOTLYAR ,  Kelin KUHN

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L21/02 ,  H01L29/40 ,  H01L29/45

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/28512 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/66477 ,  H01L29/66795

Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods/structures may include forming a source/drain region in a substrate of a device, and forming an alloy in the source/drain region, wherein the alloy comprises a material that decreases a band gap between source/drain contacts and the source/drain regions to substantially zero. The embodiments herein reduce an external parasitic resistance of the device.

Abstract translation: 描述了利用设置在源极/漏极结构中的位错形成应变通道器件的方法。 这些方法/结构可以包括在器件的衬底中形成源极/漏极区域，以及在源极/漏极区域中形成合金，其中合金包括减小源极/漏极接触点与源极/漏极接触点之间的带隙的材料， 漏极区域基本上为零。 这里的实施例减小了器件的外部寄生电阻。

公开(公告)号：US20200227520A1

公开(公告)日：2020-07-16

申请号：US16831692

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Kelin J. KUHN ,  Seiyon KIM ,  Rafael RIOS ,  Stephen M. CEA ,  Martin D. GILES ,  Annalisa CAPPELLANI ,  Titash RAKSHIT ,  Peter CHANG ,  Willy RACHMADY

IPC: H01L29/06 ,  B82Y10/00 ,  H01L21/762 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L29/165 ,  H01L27/092 ,  H01L27/12 ,  H01L29/10

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

公开(公告)号：US20200152797A1

公开(公告)日：2020-05-14

申请号：US16740089

申请日：2020-01-10

Applicant: Intel Corporation

Inventor： Stephen M. CEA ,  Annalisa CAPPELLANI ,  Martin D. GILES ,  Rafael RIOS ,  Seiyon KIM ,  Kelin J. KUHN

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06 ,  H01L21/268 ,  H01L29/78

Abstract: Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

公开(公告)号：US20200066912A1

公开(公告)日：2020-02-27

申请号：US16325164

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Van H. LE ,  Rafael RIOS ,  Shriram SHIVARAMAN ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC

IPC: H01L29/786 ,  H01L29/221 ,  H01L29/66

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing bi-layer semiconducting oxides in a source/drain for low access and contact resistance of thin film transistors. For instance, there is disclosed in accordance with one embodiment a semiconductor device having therein a substrate; a bi-layer oxides layer formed from a first oxide material and a second oxide material, the first oxide material comprising a semiconducting oxide material and having different material properties from the second oxide material comprising a high mobility oxide material; a channel layer formed atop the substrate, the channel layer formed from the semiconducting oxide material of the bi-layer oxides layer; a high mobility oxide layer formed atop the channel layer, the high conductivity oxide layer formed from the high mobility oxide material of the bi-layer oxides layer; metallic contacts formed atop the high mobility oxide layer; a gate and a gate oxide material formed atop the high mobility oxide layer, the gate oxide material being in direct contact with the high mobility oxide layer; and spacers separating the metallic contacts from the gate and gate oxide material. Other related embodiments are disclosed.

公开(公告)号：US20190252020A1

公开(公告)日：2019-08-15

申请号：US16320023

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Rafael RIOS ,  Abhishek Anil SHARMA ,  Van H. LE ,  Gilbert William DEWEY ,  Jack T. KAVALIEROS

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0007 ,  G11C8/16 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/15 ,  G11C2213/56 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1666

Abstract: A two transistor, one resistor gain cell and a suitable storage element are described. In some embodiments the gain cell has a resistive memory element coupled to a common node at one end to store a value and to a source line at another end, the value being read as conductivity between the common node and the source line of the resistive memory element, a write transistor having a source coupled to a bit line, a gate coupled to a write line, and a drain coupled to the common node to write a value at the bit line to the resistive memory element upon setting the write line high, and a read transistor having a source coupled to a bit line read line and a gate coupled to the common node to read the value written to the resistive memory element as a value at the second transistor gate.

公开(公告)号：US20190214461A1

公开(公告)日：2019-07-11

申请号：US16358613

申请日：2019-03-19

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Kelin J. KUHN ,  Tahir GHANI ,  Anand S. MURTHY ,  Mark ARMSTRONG ,  Rafael RIOS ,  Abhijit Jayant PETHE ,  Willy RACHMADY

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/306 ,  H01L29/786 ,  H01L21/3115

CPC classification number: H01L29/0673 ,  B82Y40/00 ,  H01L21/30604 ,  H01L21/3105 ,  H01L21/31155 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/78696

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

公开(公告)号：US20190172921A1

公开(公告)日：2019-06-06

申请号：US16325333

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Van H. LE ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Shriram SHIVARAMAN

IPC: H01L29/45 ,  H01L29/786 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/443

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a high mobility low contact resistance semiconducting oxide in metal contact vias for thin film transistors. For instance, there is disclosed in accordance with one embodiment an oxide semiconductor transistor, having therein: a substrate layer; a channel layer formed atop the substrate; a metal gate and a gate oxide material formed atop the semiconducting oxide material of the channel layer; spacers positioned adjacent to the gate and gate oxide material; a dielectric layer formed atop the channel layer, the dielectric layer encompassing the spacers, the gate, and the gate oxide material; contact vias opened into the dielectric material forming an opening through the dielectric layer to the channel layer; a high mobility liner material lining the contact vias and in direct contact with the channel layer, the high mobility liner formed from a high mobility oxide material; and metallic contact material filling the contact vias opened into the dielectric material and separated from the channel layer by the high mobility liner of the contact vias. Other related embodiments are disclosed.

公开(公告)号：US20180323264A1

公开(公告)日：2018-11-08

申请号：US15773549

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Van H. LE ,  Rafael RIOS ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC

IPC: H01L29/24 ,  H01L29/78 ,  H01L29/417 ,  H01L29/45 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L21/443 ,  H01L29/04

CPC classification number: H01L29/24 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/443 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/12 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/41758 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785

Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and an IGZO fin formed above the substrate. Embodiments may include a source contact and a drain contact that are formed adjacent to more than one surface of the IGZO fin. Additionally, embodiments may include a gate electrode formed between the source contact and the drain contact. The gate electrode may be separated from the IGZO layer by a gate dielectric. In one embodiment, the IGZO transistor is a fmfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

公开(公告)号：US20170271501A1

公开(公告)日：2017-09-21

申请号：US15505558

申请日：2014-09-24

Applicant: Intel Corporation

Inventor： Uygar E. AVCI ,  Rafael RIOS ,  Kelin J. KUHN ,  Ian A. YOUNG ,  Justin R. WEBER

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/16 ,  H01L29/24 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/66795 ,  H01L29/7391

Abstract: Described is a TFET comprising: a nanowire having doped regions for forming source and drain regions, and an un-doped region for coupling to a gate region; and a first termination material formed over the nanowire; and a second termination material formed over a section of the nanowire overlapping the gate and source regions. Described is another TFET comprising: a first section of a nanowire having doped regions for forming source and drain regions, and an undoped region for coupling to a gate region; a second section of the nanowire extending orthogonal to the first section, the second section formed next to the gate and source regions; and a termination material formed over the first and second sections of the nanowire.

公开(公告)号：US20170047400A1

公开(公告)日：2017-02-16

申请号：US15333123

申请日：2016-10-24

Applicant: Intel Corporation

Inventor： Seiyon Kim ,  Kelin J. KUHN ,  Tahir GHAN! ,  Anand S. MURTHY ,  Mark ARMSTRONG ,  Rafael RIOS ,  Abhijit Jayant PETHE ,  Willy RACHMADY

IPC: H01L29/06 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/3115 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/0673 ,  B82Y40/00 ,  H01L21/30604 ,  H01L21/3105 ,  H01L21/31155 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/78696

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract translation: 公开了一种具有多个内部间隔物的纳米线器件和用于形成所述内部间隔物的方法。 在一个实施例中，半导体器件包括设置在衬底上方的纳米线堆叠，纳米线堆叠具有多个垂直堆叠的纳米线，围绕多个纳米线中的每一个缠绕的栅极结构，限定器件的沟道区，栅极 结构，其具有栅极侧壁，在沟道区域的相对侧上的一对源极/漏极区域; 以及位于纳米线堆叠内部的两个相邻纳米线之间的栅极侧壁的一部分上的内部间隔物。 在一个实施例中，内部间隔物通过在与沟道区相邻蚀刻的凹坑中沉积间隔物形成。 在一个实施例中，通过沟道区蚀刻凹坑。 在另一个实施例中，通过源/漏区蚀刻凹坑。