公开(公告)号：US10923429B2

公开(公告)日：2021-02-16

申请号：US16940024

申请日：2020-07-27

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Chia-Pin Chiu ,  Aleksandar Aleksov ,  Hinmeng Au ,  Stefanie M. Lotz ,  Johanna M. Swan ,  Sujit Sharan

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/00 ,  H01L25/065 ,  H01L21/683

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

公开(公告)号：US20200006236A1

公开(公告)日：2020-01-02

申请号：US16021966

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Andrew Paul Collins ,  Jianyong Xie ,  Sujit Sharan ,  Henning Braunisch ,  Aleksandar Aleksov

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L25/065

Abstract: Embodiments may relate to an interposer that has a first layer with a plurality of first layer pads that may couple with a die. The interposer may further include a second layer with a power delivery component. The interposer may further include a very high density (VHD) layer, that has a VHD pad coupled by a first via with the power delivery component and coupled by a second via with a first layer pad. Other embodiments may be described and/or claimed.

公开(公告)号：US20190393142A1

公开(公告)日：2019-12-26

申请号：US16015739

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Andrew Collins ,  Jianyong Xie ,  Sujit Sharan

IPC: H01L23/498 ,  H01L25/16 ,  H01L49/02 ,  H01L23/42 ,  H01L21/48

Abstract: A micro-trace containing package substrate provides a low-inductance alternating-current decoupling path between a semiconductive device and a die-side capacitor.

公开(公告)号：US10475736B2

公开(公告)日：2019-11-12

申请号：US15718012

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Arnab Sarkar ,  Arghya Sain ,  Kristof Darmawikarta ,  Henning Braunisch ,  Prashant D. Parmar ,  Sujit Sharan ,  Johanna M. Swan ,  Feras Eid

IPC: H01L23/50 ,  H01L21/48 ,  H01L23/498 ,  G06F17/50 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

Abstract: Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.

公开(公告)号：US10461047B2

公开(公告)日：2019-10-29

申请号：US15749744

申请日：2015-10-29

Applicant: Intel Corporation

Inventor： Dae-Woo Kim ,  Sujit Sharan ,  Sairam Agraharam

IPC: H01L23/538 ,  H01L23/58 ,  H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/00 ,  G01R31/27 ,  H01L23/522 ,  H01L25/065 ,  H01L25/18

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semi-conductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

公开(公告)号：US10002824B2

公开(公告)日：2018-06-19

申请号：US15619463

申请日：2017-06-10

Applicant: INTEL CORPORATION

Inventor： Ankur Agrawal ,  Srinivas S. Moola ,  Sujit Sharan ,  Vijay Govindarajan

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/02

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L23/02 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/544 ,  H01L23/564 ,  H01L24/16 ,  H01L24/81 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/0401 ,  H01L2224/10135 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81141 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2924/01028 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Incorporating at least one magnetic alignment structure on a microelectronic device and incorporating at least one alignment coil within a microelectronic substrate, wherein the alignment coil may be powered to form a magnetic field to attract the magnetic alignment structure, thereby aligning the microelectronic device to the microelectronic substrate. After alignment, the microelectronic device may be electrically attached to the substrate. Embodiments may include additionally incorporating an alignment detection coil within the microelectronic substrate, wherein the alignment detection coil may be powered to form a magnetic field to detect variations in the magnetic field generated by the alignment coil in order verify the alignment of the microelectronic device to the microelectronic substrate.

公开(公告)号：US20170278783A1

公开(公告)日：2017-09-28

申请号：US15619463

申请日：2017-06-10

Applicant: INTEL CORPORATION

Inventor： Ankur Agrawal ,  Srinivas S. Moola ,  Sujit Sharan ,  Vijay Govindarajan

IPC: H01L23/498 ,  H01L23/02 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L23/02 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/544 ,  H01L23/564 ,  H01L24/16 ,  H01L24/81 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/0401 ,  H01L2224/10135 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81141 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2924/01028 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Incorporating at least one magnetic alignment structure on a microelectronic device and incorporating at least one alignment coil within a microelectronic substrate, wherein the alignment coil may be powered to form a magnetic field to attract the magnetic alignment structure, thereby aligning the microelectronic device to the microelectronic substrate. After alignment, the microelectronic device may be electrically attached to the substrate. Embodiments may include additionally incorporating an alignment detection coil within the microelectronic substrate, wherein the alignment detection coil may be powered to form a magnetic field to detect variations in the magnetic field generated by the alignment coil in order verify the alignment of the microelectronic device to the microelectronic substrate.

公开(公告)号：US09258880B2

公开(公告)日：2016-02-09

申请号：US13987701

申请日：2013-08-22

Applicant: INTEL CORPORATION

Inventor： Aleksandar Aleksov ,  Vladimir Noveski ,  Sujit Sharan ,  Shankar Ganapathysubramanian

IPC: H05H1/02 ,  H05K1/02 ,  H01L21/48 ,  H01L23/15 ,  H01L23/498 ,  H05K3/46 ,  H05K1/03 ,  H05K3/06 ,  H05K3/10 ,  H05K3/20 ,  H05K3/38

CPC classification number: H05K1/0201 ,  H01L21/4807 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/06 ,  H05K3/107 ,  H05K3/205 ,  H05K3/388 ,  H05K3/4617 ,  H05K3/4629 ,  H05K3/4647 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0376 ,  H05K2201/096 ,  H05K2201/09881 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.

公开(公告)号：US12142553B2

公开(公告)日：2024-11-12

申请号：US18138512

申请日：2023-04-24

Applicant: Intel Corporation

Inventor： Arnab Sarkar ,  Sujit Sharan ,  Dae-Woo Kim

IPC: H01L23/498 ,  H01L21/66 ,  H01L23/00 ,  H01L23/544 ,  H01L23/58 ,  H01L25/065 ,  H01L25/18

Abstract: Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure incudes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

公开(公告)号：US12044888B2

公开(公告)日：2024-07-23

申请号：US17131654

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Xiaoqian Li ,  Nitin Deshpande ,  Sujit Sharan

IPC: G02B6/42

CPC classification number: G02B6/4243 ,  G02B6/423 ,  G02B6/4239

Abstract: A groove alignment structure comprises an etch stop material and a substrate over the etch stop material. A set of grooves is along a first direction in a top surface of the substrate, and adhesive material is in a bottom of the set of grooves. Optical fibers are in the set of grooves over the adhesive material and a portion of the optical fibers extends above the substrate. A set of polymer guides is along the first direction on the top surface of the substrate interleaved with the set of grooves.