Lubricant having nanoparticles and microparticles to enhance fuel efficiency, and a laser synthesis method to create dispersed nanoparticles
    22.
    发明授权
    Lubricant having nanoparticles and microparticles to enhance fuel efficiency, and a laser synthesis method to create dispersed nanoparticles 失效
    具有纳米颗粒和微粒以提高燃料效率的润滑剂和用于产生分散的纳米颗粒的激光合成方法

    公开(公告)号:US07994105B2

    公开(公告)日:2011-08-09

    申请号:US11979529

    申请日:2007-11-05

    申请人: Jagdish Narayan

    发明人: Jagdish Narayan

    摘要: A combination nano and microparticle treatment for engines enhances fuel efficiency and life duration and reduces exhaust emissions. The nanoparticles are chosen from a class of hard materials, preferably alumina, silica, ceria, titania, diamond, cubic boron nitride, and molybdenum oxide. The microparticles are chosen from a class of materials of layered structures, preferably graphite, hexagonal boron nitride, magnesium silicates (talc) and molybdenum disulphide. The nano-micro combination can be chosen from the same materials. This group of materials includes zinc oxide, copper oxide, molybdenum oxide, graphite, talc, and hexagonal boron nitride. The ratio of nano to micro in the proposed combination varies with the engine characteristics and driving conditions. A laser synthesis method can be used to disperse nanoparticles in engine oil or other compatible medium. The nano and microparticle combination when used in engine oil can effect surface morphology changes such as smoothening and polishing of engine wear surfaces, improvement in coefficient of friction, and fuel efficiency enhancement up to 35% in a variety of vehicles (cars and trucks) under actual road conditions, and reduction in exhaust emissions up to 90%.

    摘要翻译: 用于发动机的纳米和微粒组合治疗可以提高燃油效率和使用寿命,并减少废气排放。 纳米颗粒选自一类硬质材料,优选氧化铝,二氧化硅,二氧化铈,二氧化钛,金刚石,立方氮化硼和氧化钼。 微粒选自分层结构的材料,优选石墨,六方氮化硼,硅酸镁(滑石)和二硫化钼。 纳米微组合可以从相同的材料中选择。 该组材料包括氧化锌,氧化铜,氧化钼,石墨,滑石和六方氮化硼。 所提出的组合中的纳米与微米的比值随发动机特性和驾驶条件而变化。 可以使用激光合成方法将纳米颗粒分散在发动机机油或其他兼容介质中。 在发动机油中使用的纳米和微粒组合可以影响表面形态变化,如发动机磨损表面的平滑和抛光,摩擦系数的提高和燃油效率的提高,在各种车辆(汽车和卡车)下可达35% 实际路况,废气排放量减少达90%。

    Bonding pad for gallium nitride-based light-emitting devices
    23.
    发明授权
    Bonding pad for gallium nitride-based light-emitting devices 失效
    用于氮化镓基发光器件的接合焊盘

    公开(公告)号:US07122841B2

    公开(公告)日:2006-10-17

    申请号:US10860798

    申请日:2004-06-03

    IPC分类号: H01L27/15

    摘要: A semiconductor device includes a substrate having a first major surface; a semiconductor device structure over the first surface of the substrate, the device structure comprising an n-type semiconductor layer, and a p-type semiconductor layer over the n-type semiconductor layer; a p-side electrode having a first and a second surface, wherein the first surface is in electrical contact with the p-type semiconductor layer; and a p-side bonding pad over the p-side electrode. Preferably, the semiconductor device further comprises an n-side bonding pad over an n-type semiconductor layer. The p-side and n-side bonding pads each independently includes a gold layer as its top layer and a single or multiple layers of a diffusion barrier under the top gold layer. Optionally, one or more metal layers are further included under the diffusion barrier. Typically, the p-side bonding pad is formed on the p-side electrode. The n-side bonding pad typically is formed on the n-type semiconductor layer, and forms a good ohmic contact with the n-type semiconductor layer.

    摘要翻译: 半导体器件包括具有第一主表面的衬底; 在所述衬底的第一表面上的半导体器件结构,所述器件结构包括n型半导体层和在所述n型半导体层上的p型半导体层; 具有第一表面和第二表面的p侧电极,其中所述第一表面与所述p型半导体层电接触; 以及p侧电极上的p侧接合焊盘。 优选地,半导体器件还包括在n型半导体层上的n侧焊盘。 p侧和n侧接合焊盘各自独立地包括作为其顶层的金层和在顶部金层下方的单层或多层扩散阻挡层。 任选地,在扩散阻挡层下方还包括一个或多个金属层。 通常,p侧焊盘形成在p侧电极上。 n型接合焊盘通常形成在n型半导体层上,与n型半导体层形成良好的欧姆接触。

    Light-emitting diode device geometry
    25.
    发明授权
    Light-emitting diode device geometry 失效
    发光二极管器件几何

    公开(公告)号:US06847052B2

    公开(公告)日:2005-01-25

    申请号:US10463219

    申请日:2003-06-17

    摘要: A semiconductor device includes: a substrate; an n-type semiconductor layer over the substrate, the n-type semiconductor layer having a planar top surface; a p-type semiconductor layer extending over a major portion of the n-type semiconductor layer and not extending over an exposed region of the n-type semiconductor layer located adjacent to at least one edge of the planar top surface of the n-type semiconductor layer; a first bonding pad provided on the exposed region of the n-type semiconductor layer; an electrode layer extending over the p-type semiconductor layer; and a second bonding pad on the electrode layer, the bonding pad including a central region for securing an electrical interconnect, and at least one finger-like region protruding from the central region, the finger-like region having a length extending away from the central region and a width that is substantially less than the length. A method for producing a semiconductor device also is described.

    摘要翻译: 半导体器件包括:衬底; 在该衬底上的n型半导体层,该n型半导体层具有平坦的顶表面; p型半导体层,其延伸在n型半导体层的主要部分上,并且不延伸在邻近n型半导体的平面顶表面的至少一个边缘的n型半导体层的暴露区域上 层; 设置在所述n型半导体层的所述露出区域上的第一焊盘; 在p型半导体层上延伸的电极层; 以及在所述电极层上的第二焊盘,所述焊盘包括用于固定电互连的中心区域和从所述中心区域突出的至少一个指状区域,所述指状区域具有远离所述中心部分的长度 区域和宽度明显小于长度。 还描述了一种半导体器件的制造方法。

    Electrode for p-type gallium nitride-based semiconductors
    26.
    发明授权
    Electrode for p-type gallium nitride-based semiconductors 失效
    p型氮化镓基半导体电极

    公开(公告)号:US06734091B2

    公开(公告)日:2004-05-11

    申请号:US10187465

    申请日:2002-06-28

    IPC分类号: H01L2128

    摘要: An improved electrode for a p-type gallium nitride based semiconductor material is disclosed that includes a layer of an oxidized metal and a first and a second layer of a metallic material. The electrode is formed by depositing three or more metallic layers over the p-type semiconductor layer such that at least one metallic layer is in contact with the p-type semiconductor layer. At least two of the metallic layers are then subjected to an annealing treatment in the presence of oxygen to oxidize at least one of the metallic layers to form a metal oxide. The electrodes provide good ohmic contacts to p-type gallium nitride-based semiconductor materials and, thus, lower the operating voltage of gallium nitride-based semiconductor devices.

    摘要翻译: 公开了一种用于p型氮化镓基半导体材料的改进的电极,其包括氧化金属层和金属材料的第一和第二层。 电极通过在p型半导体层上沉积三个或更多个金属层而形成,使得至少一个金属层与p型半导体层接触。 然后至少两个金属层在氧的存在下进行退火处理以氧化至少一个金属层以形成金属氧化物。 电极为p型氮化镓基半导体材料提供良好的欧姆接触,从而降低氮化镓基半导体器件的工作电压。

    Method for making optoelectronic and microelectronic devices including cubic ZnMgO and/or CdMgO alloys
    27.
    发明授权
    Method for making optoelectronic and microelectronic devices including cubic ZnMgO and/or CdMgO alloys 有权
    制造包括立方晶ZnMgO和/或CdMgO合金的光电子和微电子器件的方法

    公开(公告)号:US06518077B2

    公开(公告)日:2003-02-11

    申请号:US10050077

    申请日:2002-01-15

    IPC分类号: H01L2100

    摘要: An electronic device has an alloy layer containing magnesium oxide and at least one of zinc oxide and cadmium oxide and having a cubic structure on a substrate. The alloy layer may be directly on the substrate or, alternatively, one or more buffer layers may be between the alloy layer and the substrate. The alloy layer may be domain-matched epitaxially grown directly on the substrate, or may be lattice-matched epitaxially grown directly on the buffer layer. The cubic layer may also be used to form single and multiple quantum wells. Accordingly, electronic devices having wider bandgap, increased binding energy of excitons, and/or reduced density of growth and/or misfit dislocations in the active layers as compared with conventional III-nitride electronic devices may be provided.

    摘要翻译: 电子器件具有包含氧化镁和氧化锌和氧化镉中的至少一种并且在衬底上具有立方结构的合金层。 合金层可以直接在衬底上,或者,一个或多个缓冲层可以在合金层和衬底之间。 合金层可以直接在衬底上外延生长,或者可以直接在缓冲层上外延生长的晶格匹配。 立方体层也可用于形成单个和多个量子阱。 因此,与传统的III族氮化物电子器件相比,可以提供具有更宽的带隙,增加的激子的结合能和/或有源层中生长和/或失配位错密度的电子器件。

    Optoelectronic and microelectronic devices including cubic ZnMgO and/or CdMgO alloys
    28.
    发明授权
    Optoelectronic and microelectronic devices including cubic ZnMgO and/or CdMgO alloys 有权
    包括立方ZnMgO和/或CdMgO合金的光电子和微电子器件

    公开(公告)号:US06423983B1

    公开(公告)日:2002-07-23

    申请号:US09687519

    申请日:2000-10-13

    IPC分类号: H01L3300

    摘要: An electronic device has an alloy layer containing magnesium oxide and at least one of zinc oxide and cadmium oxide and having a cubic structure on a substrate. The alloy layer may be directly on the substrate or, alternatively, one or more buffer layers may be between the alloy layer and the substrate. The alloy layer may be domain-matched epitaxially grown directly on the substrate, or may be lattice-matched epitaxially grown directly on the buffer layer. The cubic layer may also be used to form single and multiple quantum wells. Accordingly, electronic devices having wider bandgap, increased binding energy of excitons, and/or reduced density of growth and/or misfit dislocations in the active layers as compared with conventional III-nitride electronic devices may be provided.

    摘要翻译: 电子器件具有包含氧化镁和氧化锌和氧化镉中的至少一种并且在衬底上具有立方结构的合金层。 合金层可以直接在衬底上,或者,一个或多个缓冲层可以在合金层和衬底之间。 合金层可以直接在衬底上外延生长,或者可以直接在缓冲层上外延生长的晶格匹配。 立方体层也可用于形成单个和多个量子阱。 因此,与传统的III族氮化物电子器件相比,可以提供具有更宽的带隙,增加的激子的结合能和/或有源层中生长和/或失配位错密度的电子器件。

    Dislocation density reduction in gallium arsenide on silicon
heterostructures
    29.
    发明授权
    Dislocation density reduction in gallium arsenide on silicon heterostructures 失效
    硅异质结构中砷化镓的位错密度降低

    公开(公告)号:US5208182A

    公开(公告)日:1993-05-04

    申请号:US790356

    申请日:1991-11-12

    IPC分类号: H01L21/20 H01L21/324

    摘要: A method of forming gallium arsenide on silicon heterostructure including the use of strained layer superlattices in combination with rapid thermal annealing to achieve a reduced threading dislocation density in the epilayers. Strain energy within the superlattices causes threading dislocations to bend, preventing propagation through the superlattices to the epilayer. Rapid thermal annealing causes extensive realignment and annihilation of dislocations of opposite Burgers vectors and a further reduction of threading dislocations in the epilayer.

    摘要翻译: 一种在硅异质结构上形成砷化镓的方法,包括使用应变层超晶格与快速热退火相结合,以实现外延层中的穿透位错密度降低。 超晶格内的应变能导致穿透位错弯曲,防止通过超晶格传播到外延层。 快速热退火导致相反的汉堡载体的位错的广泛重排和消除,并进一步减少外延层中的穿线位错。

    High transition temperature superconductors
    30.
    发明授权
    High transition temperature superconductors 失效
    高转变温度超导体

    公开(公告)号:US5063202A

    公开(公告)日:1991-11-05

    申请号:US517523

    申请日:1990-04-27

    申请人: Jagdish Narayan

    发明人: Jagdish Narayan

    IPC分类号: C04B35/45 H01L39/12

    摘要: The phase of the YBa.sub.2 Cu.sub.3 O.sub.9-.delta. having a perovskite unit cell structure of approximately the following dimensions a=3.8A, b=3.9A, and c=13.55A has been discovered and identified.

    摘要翻译: 已经发现和鉴定了具有大致以下尺寸a = 3.8A,b = 3.9A和c = 13.55A的钙钛矿晶胞结构的YBa2Cu3O9-δ的相位。