公开(公告)号：US20210082823A1

公开(公告)日：2021-03-18

申请号：US16807835

申请日：2020-03-03

Applicant: KIOXIA CORPORATION

Inventor： Nobuyuki MOMO ,  Keisuke NAKATSUKA

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/482 ,  H01L49/02

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip including a first metal pad and a second metal pad; and a second semiconductor chip including a third metal pad and a fourth metal pad, the third metal pad joined to the first metal pad, the fourth metal pad coupled to the second metal pad via a dielectric layer, wherein the second semiconductor chip is coupled to the first semiconductor chip via the first metal pad and the third metal pad.

公开(公告)号：US20210074638A1

公开(公告)日：2021-03-11

申请号：US17015868

申请日：2020-09-09

Applicant: Kioxia Corporation

Inventor： Tomoya SANUKI ,  Keisuke NAKATSUKA ,  Yasuhito YOSHIMIZU

IPC: H01L23/535 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00

Abstract: In one embodiment, a semiconductor device includes a substrate including two element regions that extend in a first direction parallel to a surface of the substrate and are adjacent to each other in a second direction crossing the first direction. The device further includes an interconnection layer provided above the substrate. The device further includes an insulator provided between the substrate and the interconnection layer. The device further includes a plug extending in the second direction and in a third direction crossing the first and second directions in the insulator, provided on each of the element regions, and electrically connected to the element regions and the interconnection layer.

公开(公告)号：US20240315037A1

公开(公告)日：2024-09-19

申请号：US18599586

申请日：2024-03-08

Applicant: Kioxia Corporation

Inventor： Keita HASEGAWA ,  Keisuke NAKATSUKA ,  Koichi SAKATA

IPC: H10B43/35 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B43/35 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0657 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50 ,  H01L2225/06541

Abstract: A semiconductor device includes a first chip including a peripheral circuit, and a second chip bonded to the first chip. The second chip includes a stacked body, a contact, a first column-shaped part, a second conductive layer, and a second column-shaped part. The contact is connected to a staircase part of the stacked body. The first column-shaped part is formed to extend through a memory part of the stacked body in a first direction and forms a memory cell transistor at an intersection part with a first conductive layer. The second conductive layer is formed above the stacked body and connected to an upper end part of the first column-shaped part. The second column-shaped part is formed to extend through the staircase part in the first direction. The second column-shaped part is electrically insulated from the second conductive layer.

公开(公告)号：US20230410915A1

公开(公告)日：2023-12-21

申请号：US18177115

申请日：2023-03-02

Applicant: Kioxia Corporation

Inventor： Tomoya SANUKI ,  Keisuke NAKATSUKA

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/26 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor storage device has a bit line, a source line, a first memory cell and a second memory cell provided between the bit line and the source line and connected in series, a first word line connected to the first memory cell, a second word line connected to the second memory cell, and a control circuit. The control circuit, when executing a read operation with respect to the first memory cell, supplies a source voltage to the source line, supplies a first voltage to the first word line, and supplies a second voltage to the second word line, and a difference between the source voltage and the second voltage is smaller than a difference between the source voltage and the first voltage.

公开(公告)号：US20230397446A1

公开(公告)日：2023-12-07

申请号：US18179976

申请日：2023-03-07

Applicant: Kioxia Corporation

Inventor： Hiroshi NAKAKI ,  Keisuke NAKATSUKA

IPC: H10B80/00 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

CPC classification number: H10B80/00 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26

Abstract: According to an embodiment, a semiconductor memory device includes a first memory cell array, a second memory cell array, and a row decoder. The first memory cell array includes a first select transistor, a first memory cell, a second select transistor, a first word line, a first select gate line, and a second select gate line. The second memory cell array includes, a third select transistor, a second memory cell, a fourth select transistor, a second word line, a third select gate line, a fourth select gate line. The first word line and the second word line are commonly coupled to the row decoder. The first select gate line, the second select gate line, the third select gate line, and the fourth select gate line are separately coupled to the row decoder.

公开(公告)号：US20230005957A1

公开(公告)日：2023-01-05

申请号：US17942009

申请日：2022-09-09

Applicant: Kioxia Corporation

Inventor： Keisuke NAKATSUKA

IPC: H01L27/11582 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  G11C16/04 ,  G11C16/26

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a first conductor layer, second conductor layers, a first semiconductor layer, a pillar, and a contact. The pillar has a portion provided to penetrate the second conductor layers and the first semiconductor layer. The contact is electrically connected to the pillar and the first conductor layer. The pillar includes a second semiconductor layer, a first insulator layer provided at least between the second semiconductor layer and the second conductor layers, and a third semiconductor layer provided between the second semiconductor layer and the first semiconductor layer and in contact with each of the second semiconductor layer and the first semiconductor layer.

公开(公告)号：US20210296331A1

公开(公告)日：2021-09-23

申请号：US17011006

申请日：2020-09-03

Applicant: Kioxia Corporation

Inventor： Naoya YOSHIMURA ,  Keisuke NAKATSUKA

IPC: H01L27/11519 ,  H01L27/11565

Abstract: A semiconductor storage device includes first conductive layers stacked in a first direction and extend in a second direction; second conductive layers stacked in the first direction and extend in the second direction; third conductive layers that are electrically connected to the first conductive layers and the second conductive layers and stacked in the first direction; a first insulating layer and a second insulating layer sandwich the first conductive layer; a third insulating layer and a fourth insulating layer sandwich the second conductive layer; first pillars arranged in the second direction in the first insulating layer with a first distance; and second pillars arranged in the second direction in the second insulating layer with the first distance. Each of the second pillars is displaced from a corresponding one of the first pillars by a second distance that is shorter than a half of the first distance in the second direction.

公开(公告)号：US20240315019A1

公开(公告)日：2024-09-19

申请号：US18671074

申请日：2024-05-22

Applicant: Kioxia Corporation

Inventor： Hideto TAKEKIDA ,  Yosuke MURAKAMI ,  Keisuke NAKATSUKA ,  Yefei HAN

IPC: H10B43/10 ,  H10B43/20 ,  H10B43/50

CPC classification number: H10B43/10 ,  H10B43/20 ,  H10B43/50

Abstract: A semiconductor storage device of an embodiment includes a first conductive layer, a second conductive layer, a first conductive pillar, a first semiconductor layer, and a first storage layer. The first conductive layer extends in a first direction. The second conductive layer is along the first conductive layer in a third direction intersecting the first direction. The second conductive layer extends in the first direction. The first conductive pillar penetrates the first conductive layer and the second conductive layer in the third direction. The first semiconductor layer is in contact with the first conductive layer and the second conductive layer. The first semiconductor layer faces the first conductive pillar in the first direction. The first storage layer is between the first semiconductor layer and the first conductive pillar.

公开(公告)号：US20230395500A1

公开(公告)日：2023-12-07

申请号：US18181851

申请日：2023-03-10

Applicant: Kioxia Corporation

Inventor： Keisuke NAKATSUKA ,  Yasuhiro UCHIYAMA

IPC: H01L23/528 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  H01L23/522 ,  H10B80/00 ,  H10B43/10 ,  H10B43/20 ,  H10B41/10 ,  H10B41/20 ,  H01L25/18

CPC classification number: H01L23/5283 ,  G11C16/26 ,  G11C16/0483 ,  G11C16/10 ,  H01L23/5226 ,  H10B80/00 ,  H10B43/10 ,  H10B43/20 ,  H10B41/10 ,  H10B41/20 ,  H01L25/18

Abstract: According to one embodiment, there is provided a semiconductor memory device including a first chip, a second chip and a third chip. In the first chip, plural first conductive layers are stacked via a first insulating layer. In the second chip, plural second conductive layers are stacked via a second insulating layer. A number of stack layers in the plural first conductive layers and a number of stack layers in the plural second conductive layers are different from each other.

公开(公告)号：US20230307396A1

公开(公告)日：2023-09-28

申请号：US17901448

申请日：2022-09-01

Applicant: Kioxia Corporation

Inventor： Yasunori IWASHITA ,  Shinya ARAI ,  Keisuke NAKATSUKA ,  Hiroaki ASHIDATE

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/06 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/06517 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511 ,  H01L2924/3511

Abstract: A semiconductor device includes a first stacked body and a second stacked body bonded to the first stacked body. The first stacked body includes a first pad provided on a first bonding surface to which the first stacked body and the second stacked body are bonded. The second stacked body includes a second pad bonded to the first pad on the first bonding surface. When a direction from the first stacked body to the second stacked body is defined as a first direction, a direction intersecting with the first direction is defined as a second direction, a direction intersecting with the first direction and the second direction is defined as a third direction, dimensions of the first pad and the second pad in the third direction are defined as PX1 and PX2, respectively, and dimensions of the first pad and the second pad in the second direction are defined as PY1 and PY2, respectively, the dimensions of the first pad and the second pad satisfy at least one of Equations (1) and (2) below.


PX1>PY1   (1)



PY2>PX2   (2)