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    Etching openings of different depths using a single mask layer method and structure
    22.
    发明授权
    Etching openings of different depths using a single mask layer method and structure 失效
    使用单一掩模层方法和结构蚀刻不同深度的开口

    公开(公告)号：US06887785B1

    公开(公告)日：2005-05-03

    申请号：US10709564

    申请日：2004-05-13

    申请人： David M. Dobuzinsky ,  Carl J. Radens ,  Roy C. Iggulden ,  Jay W. Strane ,  Keith K. H. Wong

    发明人： David M. Dobuzinsky ,  Carl J. Radens ,  Roy C. Iggulden ,  Jay W. Strane ,  Keith K. H. Wong

    IPC分类号： H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/76844 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76897

    摘要： A semiconductor device with openings of differing depths in a substrate or layer is described, as are related methods for its manufacture. Through selective deposition of a single mask layer, whereby low aspect ratio openings are substantially coated while high aspect ratio are at most partially coated, subsequent etching of the substrate or layer is restricted to uncoated portions of the high aspect ratio openings. The result is a substrate or layer with openings of more than one depth using a single mask layer. In a second embodiment, the selective deposition of a single mask layer is utilized to etch a layer while protecting underlying structures from etching. In a third embodiment, the selective deposition of a single mask layer is utilized to etch an opening into a layer wherein the opening has a sub-lithographic diameter, i.e., the diameter of the opening is smaller than can be achieved with the particular lithographic technique employed.

    摘要翻译： 描述了在衬底或层中具有不同深度的开口的半导体器件，以及用于其制造的相关方法。 通过选择性沉积单个掩模层，由此在高纵横比最多部分涂覆的同时基本上涂覆低纵横比的开口，随后对衬底或层的蚀刻被限制在高纵横比开口的未涂覆部分。 结果是使用单个掩模层的具有多于一个深度的开口的基底或层。 在第二实施例中，使用单个掩模层的选择性沉积来蚀刻层，同时保护下面的结构免受蚀刻。 在第三实施例中，使用单个掩模层的选择性沉积来将开口蚀刻到其中开口具有亚光刻直径的开口，即，开口的直径小于可以用特定光刻技术实现的开口的直径 雇用。

    Fluorinated silicon nitride films
    23.
    发明授权
    Fluorinated silicon nitride films 失效
    氟化氮化硅膜

    公开(公告)号：US5539154A

    公开(公告)日：1996-07-23

    申请号：US429449

    申请日：1995-04-27

    申请人： Son V. Nguyen ,  David M. Dobuzinsky ,  Douglas J. Dopp ,  David L. Harmon

    发明人： Son V. Nguyen ,  David M. Dobuzinsky ,  Douglas J. Dopp ,  David L. Harmon

    IPC分类号： C23C14/06 ,  C23C16/34 ,  C23C16/505 ,  C30B25/02 ,  H01L21/318 ,  H01C7/10

    CPC分类号： C23C16/505 ,  C23C16/345

    摘要： A plasma enhanced chemical vapor deposition process for producing a fluorinated silicon nitride film on a substrate is disclosed. The process utilizes a mixture of silane, perfluorosilane and nitrogen to produce films of high conformality and stability. The silane and perfluorosilane in the mixture are in a ratio of 0.05 to 1 on a volume basis. The preferred silane is SiH.sub.4 and the preferred perfluorosilane is SiF.sub.4. Films prepared by the process are disclosed and their properties are described.

    摘要翻译： 公开了一种用于在衬底上生产氟化氮化硅膜的等离子体增强化学气相沉积工艺。 该方法利用硅烷，全氟硅烷和氮气的混合物来生产具有高共形性和稳定性的薄膜。 混合物中的硅烷和全氟硅烷的体积比为0.05-1。 优选的硅烷是SiH 4，优选的全氟硅烷是SiF 4。 公开了通过该方法制备的膜，并描述了它们的性质。

    VERTICAL SOI TRENCH SONOS CELL
    25.
    发明申请
    VERTICAL SOI TRENCH SONOS CELL 有权
    垂直SOI TRENCH SONOS电池

    公开(公告)号：US20090158234A1

    公开(公告)日：2009-06-18

    申请号：US11955913

    申请日：2007-12-13

    申请人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

    发明人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

    IPC分类号： G06F17/50

    CPC分类号： H01L29/42352 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

    摘要： A semiconductor memory device and a design structure including the semiconductor memory device embodied in a machine readable medium is provided. In particular the present invention includes a semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.

    摘要翻译： 提供半导体存储器件和包括体现在机器可读介质中的半导体存储器件的设计结构。 特别地，本发明包括其中在绝缘体上半导体（SOI）衬底中产生垂直沟槽半导体 - 氧化物 - 氮化物 - 氧化物 - 半导体（SONOS）存储单元的半导体存储器件，其允许将 基于SOI的互补金属氧化物半导体（CMOS）技术中的致密非易失性随机存取存储器（NVRAM）单元。 使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。

    STI formation in semiconductor device including SOI and bulk silicon regions
    26.
    发明授权
    STI formation in semiconductor device including SOI and bulk silicon regions 失效
    在包括SOI和体硅区域的半导体器件中形成STI

    公开(公告)号：US07118986B2

    公开(公告)日：2006-10-10

    申请号：US10710060

    申请日：2004-06-16

    申请人： Michael D. Steigerwalt ,  Mahender Kumar ,  Herbert L. Ho ,  David M. Dobuzinsky ,  Johnathan E. Faltermeier ,  Denise Pendleton

    发明人： Michael D. Steigerwalt ,  Mahender Kumar ,  Herbert L. Ho ,  David M. Dobuzinsky ,  Johnathan E. Faltermeier ,  Denise Pendleton

    IPC分类号： H01L21/76

    CPC分类号： H01L21/7624 ,  H01L21/3081 ,  H01L21/31612 ,  H01L21/76283

    摘要： Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.

    摘要翻译： 公开了在绝缘体上硅（SOI）区域和体硅区域中形成或蚀刻硅沟槽隔离（STI）的方法以及如此形成的半导体器件。 可以通过使用STI掩模蚀刻到最上层的硅层，同时在SOI和体硅区域中蚀刻STI，进行蚀刻到体硅区域中期望深度并停止在SOI区域的埋入绝缘体上的定时蚀刻 ，并蚀刻穿过SOI区域的埋层绝缘体。 用于该过程的掩埋绝缘体蚀刻可以以很少的复杂性作为硬掩模去除步骤的一部分来完成。 此外，通过为体区和SOI区域选择相同的深度，避免了后续CMP工艺的问题。 本发明还清除了可能存在氮化硅残留的SOI和体区之间的边界。

    Self-aligned borderless contacts
    27.
    发明授权
    Self-aligned borderless contacts 有权

    公开(公告)号：US06809027B2

    公开(公告)日：2004-10-26

    申请号：US10165264

    申请日：2002-06-06

    申请人： Jay W. Strane ,  Hiroyuki Akatsu ,  David M. Dobuzinsky

    发明人： Jay W. Strane ,  Hiroyuki Akatsu ,  David M. Dobuzinsky

    IPC分类号： H01L214763

    CPC分类号： H01L21/76897

    摘要： A method for forming high-density self-aligned contacts and interconnect structures in a semiconductor device. A dielectric layer thick enough to contain both interconnect and contact structures is formed on a substrate. A patterned hardmask is formed on the dielectric layer to define both the interconnect and contact structures. The openings for interconnect features are first formed by partially etching the dielectric layer selective to the hardmask. A second mask (e.g., a resist) is used to define the contact openings, and the dielectric layer is etched through the second mask, also selective to the hardmask, to expose the diffusion regions to be contacted. The patterned hardmask is used to help define the contact openings. Conductive material is then deposited in the openings which results in contacts and interconnects that are self-aligned. By first forming the openings for both interconnect and contacts, savings in processing steps may be obtained.

    Method for reducing stress in the metallization of an integrated circuit
    30.
    发明授权
    Method for reducing stress in the metallization of an integrated circuit 失效
    降低集成电路金属化应力的方法

    公开(公告)号：US5939335A

    公开(公告)日：1999-08-17

    申请号：US3107

    申请日：1998-01-06

    申请人： Kenneth C. Arndt ,  Richard A. Conti ,  David M. Dobuzinsky ,  Laertis Economikos ,  Jeffrey P. Gambino ,  Peter D. Hoh ,  Chandrasekhar Narayan

    发明人： Kenneth C. Arndt ,  Richard A. Conti ,  David M. Dobuzinsky ,  Laertis Economikos ,  Jeffrey P. Gambino ,  Peter D. Hoh ,  Chandrasekhar Narayan

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/336

    CPC分类号： H01L21/76804 ,  H01L21/32136 ,  H01L21/76835 ,  H01L21/76885

    摘要： The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.

    摘要翻译： 通过使与金属图案化方法（例如反应离子蚀刻（RIE）和镶嵌技术）一起制造的集成电路的电介质中通常感应的应力可以通过将与形成为集成电路的一部分的特征相关联的下角 在施加外部（即钝化）层之前，例如，互连）。 关于通过金属RIE工艺形成的金属线的形成，可以使用包括产生垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤的两步金属蚀刻工艺来实现这种角圆化 或者沿着垂直侧壁的下部产生锥形间隔物。 这导致圆角的底角，其改善了上覆电介质的台阶覆盖，从而消除了裂纹的可能性。 对于由大马士革图案化的金属线，可以使用包括产生垂直侧壁的第一步骤的两步沟槽蚀刻工艺，以及沿着垂直侧壁的下部产生锥形侧壁的第二步骤来实现这种角落圆化。