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44 条记录 (耗时 0.026 秒)

    FinFET having suppressed parasitic device characteristics
    21.
    发明授权
    FinFET having suppressed parasitic device characteristics 有权
    FinFET抑制寄生器件特性

    公开(公告)号：US06992354B2

    公开(公告)日：2006-01-31

    申请号：US10604086

    申请日：2003-06-25

    申请人： Edward J. Nowak ,  BethAnn Rainey

    发明人： Edward J. Nowak ,  BethAnn Rainey

    IPC分类号： H01L31/0392

    CPC分类号： H01L29/785 ,  H01L27/1203 ,  H01L29/66795

    摘要： A finFET (100) having sidwall spacers (136, 140) to suppress parasitic devices in the upper region of a channel and at the bases of source(s) and drain(s) that are artifacts of the fabrication techniques used to make the finFET. The FinFET is formed on an SOI wafer (104) by etching through a hardmask (148) so as to form a freestanding fin (120). Prior to doping the source(s) (124) and drain(s) (128), a layer (156) of thermal oxide is deposited over the entire finFET. This layer is etched away so as to form the sidewall spacers at each reentrant corner formed where a horizontal surface meets a vertical surface. Sidewall spacers (136) inhibit doping of the upper region of source(s) and drain(s) immediately adjacent the gate. Sidewall spacers (140) fill in any undercut regions (144) of BOX layer (116) that may have been formed during prior fabrication steps.

    摘要翻译： 具有侧壁间隔物（136,140）的finFET（100），其用于抑制通道上部区域中的寄生器件，以及源极和漏极的基础，这些器件是用于制造鳍状FET的制造技术的假象 。 FinFET通过蚀刻穿过硬掩模（148）形成在SOI晶片（104）上，以形成独立散热片（120）。 在掺杂源极（124）和漏极（128）之前，在整个finFET上沉积热氧化物层（156）。 该层被蚀刻掉，以便在形成的水平表面与垂直表面相交的每个折入角处形成侧壁间隔物。 侧壁间隔物（136）抑制源极的上部区域和与栅极紧邻的漏极的掺杂。 侧壁间隔物（140）填充可能在先前制造步骤期间形成的BOX层（116）的任何底切区域（144）。

    Semiconductor device having freestanding semiconductor layer
    24.
    发明授权
    Semiconductor device having freestanding semiconductor layer 有权
    具有独立半导体层的半导体器件

    公开(公告)号：US07709892B2

    公开(公告)日：2010-05-04

    申请号：US11426698

    申请日：2006-06-27

    申请人： Brent A. Anderson ,  Edward J. Nowak ,  BethAnn Rainey

    发明人： Brent A. Anderson ,  Edward J. Nowak ,  BethAnn Rainey

    IPC分类号： H01L29/94 ,  H01L27/88

    CPC分类号： H01L21/02595 ,  H01L21/02667 ,  H01L21/2022 ,  H01L29/66795 ,  H01L29/785

    摘要： A method of providing a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon device includes forming an amorphous or polycrystalline mandrel on a monocrystalline base structure. A conformal polycrystalline semiconductor layer is then formed on the mandrel and on the base structure, wherein the polycrystalline layer contacts the base structure. The polycrystalline semiconductor layer is then recrystallized so that it has a crystallinity substantially similar to that of the base structure. Thus, a freestanding semiconductor layer is formed with a high degree of control of the thickness and height thereof and maintaining a uniformity of thickness.

    摘要翻译： 在传统的SOI或体衬底硅器件上提供独立半导体层的方法包括在单晶基底结构上形成非晶或多晶心轴。 然后在心轴和基底结构上形成共形多晶半导体层，其中多晶层接触基底结构。 然后将多晶半导体层重结晶，使其具有与基础结构基本相似的结晶度。 因此，以高度控制其厚度和高度的方式形成独立的半导体层并保持厚度的均匀性。

    Methods for lateral current carrying capability improvement in semiconductor devices
    25.
    发明授权
    Methods for lateral current carrying capability improvement in semiconductor devices 失效
    半导体器件横向载流能力改善方法

    公开(公告)号：US07453151B2

    公开(公告)日：2008-11-18

    申请号：US11460314

    申请日：2006-07-27

    申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

    发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

    IPC分类号： H01L29/80

    CPC分类号： H01L21/76838 ,  H01L21/8249 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure and methods for forming the same. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

    摘要翻译： 半导体结构及其形成方法。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

    Method of forming freestanding semiconductor layer
    27.
    发明授权
    Method of forming freestanding semiconductor layer 失效
    形成独立半导体层的方法

    公开(公告)号：US07087506B2

    公开(公告)日：2006-08-08

    申请号：US10604116

    申请日：2003-06-26

    申请人： Brent A Anderson ,  Edward J Nowak ,  BethAnn Rainey

    发明人： Brent A Anderson ,  Edward J Nowak ,  BethAnn Rainey

    IPC分类号： H01L21/324

    CPC分类号： H01L21/02595 ,  H01L21/02667 ,  H01L21/2022 ,  H01L29/66795 ,  H01L29/785

    摘要： A method of providing a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon device includes forming an amorphous or polycrystalline mandrel on a monocrystalline base structure. A conformal polycrystalline semiconductor layer is then formed on the mandrel and on the base structure, wherein the polycrystalline layer contacts the base structure. The polycrystalline semiconductor layer is then recrystallized so that it has a crystallinity substantially similar to that of the base structure. Thus, a freestanding semiconductor layer is formed with a high degree of control of the thickness and height thereof and maintaining a uniformity of thickness.

    摘要翻译： 在传统的SOI或体衬底硅器件上提供独立半导体层的方法包括在单晶基底结构上形成非晶或多晶心轴。 然后在心轴和基底结构上形成共形多晶半导体层，其中多晶层接触基底结构。 然后将多晶半导体层重结晶，使其具有与基础结构基本相似的结晶度。 因此，以高度控制其厚度和高度的方式形成独立的半导体层并保持厚度的均匀性。

    Methods of base formation in a BiCMOS process
    28.
    发明申请
    Methods of base formation in a BiCMOS process 失效
    BiCMOS工艺中碱形成的方法

    公开(公告)号：US20060017066A1

    公开(公告)日：2006-01-26

    申请号：US11231385

    申请日：2005-09-21

    申请人： Peter Geiss ,  Marwan Khater ,  Qizhi Liu ,  Randy Mann ,  Robert Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas Stricker

    发明人： Peter Geiss ,  Marwan Khater ,  Qizhi Liu ,  Randy Mann ,  Robert Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas Stricker

    IPC分类号： H01L31/109

    CPC分类号： H01L29/66242 ,  H01L21/28518 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0804 ,  H01L29/456 ,  H01L29/7371

    摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.

    摘要翻译： 提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。 在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。 本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。 凸起的外基极上面的硅化物以自对准的方式延伸到发射极。 发射极通过间隔物与硅化物分离。

    Simultaneously formed isolation trench and through-box contact for silicon-on-insulator technology
    30.
    发明授权
    Simultaneously formed isolation trench and through-box contact for silicon-on-insulator technology 有权
    同时形成隔离沟槽和绝缘体上硅技术的通孔接触

    公开(公告)号：US08021943B2

    公开(公告)日：2011-09-20

    申请号：US12625701

    申请日：2009-11-25

    申请人： Alan B. Botula ,  BethAnn Rainey ,  Daniel S. Vanslette

    发明人： Alan B. Botula ,  BethAnn Rainey ,  Daniel S. Vanslette

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/743 ,  H01L21/76224 ,  H01L21/76232

    摘要： A semiconductor fabrication method comprises providing a structure which includes a semiconductor substrate having a plurality of subsurface layers, the substrate comprising a top surface and the subsurface layers comprising a top subsurface layer below the top surface of the substrate. A protective material is patterned on the top surface of the device and a material removal process is performed to simultaneously form a contact trench and an isolation trench, the material removal process removing at least a portion of the top surface and the top subsurface layer such that the contact trench and the isolation trench are formed within the subsurface layer. An insulator is then formed within the isolation trench and the contact trench is lined with the insulator. The contact trench is then filled with a conductive material such that the conductive material is deposited over the insulator.

    摘要翻译： 半导体制造方法包括提供包括具有多个次表面层的半导体衬底的结构，所述衬底包括顶表面，并且所述表面下层包括在所述衬底的顶表面下方的顶部表面层。 保护材料被图案化在器件的顶表面上，并且执行材料去除工艺以同时形成接触沟槽和隔离沟槽，所述材料去除工艺去除顶表面和顶部表面下层的至少一部分，使得 接触沟槽和隔离沟槽形成在地下层内。 然后在隔离沟槽内形成绝缘体，并且接触沟槽衬有绝缘体。 然后用导电材料填充接触沟槽，使得导电材料沉积在绝缘体上。