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公开(公告)号：US06967072B2
公开(公告)日：2005-11-22
申请号：US09921938
申请日：2001-08-02
IPC分类号： B01J19/08 , C23C16/26 , C23C16/46 , G03C5/00 , G03F7/075 , G03F7/09 , H01L21/027 , H01L21/283 , H01L21/311 , H01L21/312 , H01L21/314 , H01L21/316 , H01L21/3205 , H01L21/768 , G03F7/004 , G03F7/085
CPC分类号： H01L21/31144 , G03F7/0757 , G03F7/091 , H01L21/0276 , H01L21/76802 , H01L21/76825 , H01L21/76832
摘要： A method for forming a patterned amorphous carbon layer in a semiconductor stack, including forming an amorphous carbon layer on a substrate and forming a silicon containing photoresist layer on top of the amorphous carbon layer. Thereafter, the method includes developing a pattern transferred into the resist layer with a photolithographic process and etching through the amorphous carbon layer in at least one region defined by the pattern in the resist layer, wherein a resist layer hard mask is formed in an outer portion of the photoresist layer during etching.
摘要翻译： 一种在半导体堆叠中形成图案化的非晶碳层的方法，包括在基底上形成无定形碳层，并在无定形碳层的顶部形成含硅光致抗蚀剂层。 此后，该方法包括通过光刻工艺显影转印到抗蚀剂层中的图案，并且在由抗蚀剂层中的图案限定的至少一个区域中通过无定形碳层进行蚀刻，其中在外部形成抗蚀剂层硬掩模 的光刻胶层。
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公开(公告)号：US20160375492A1
公开(公告)日：2016-12-29
申请号：US15188799
申请日：2016-06-21
CPC分类号： B33Y40/00 , B22F3/1055 , B22F2003/1056 , B22F2999/00 , B33Y10/00 , B33Y30/00 , B33Y50/02 , Y02P10/295 , B22F2202/05
摘要： An additive manufacturing system includes a support, a dispenser to deliver a layer of metallic powder onto the support or an underlying layer on the support, an energy source to fuse at least a portion of the layer of metallic powder, and a magnet positioned and configured to apply a magnetic field to the portion of the layer of metallic powder as the layer is fused.
摘要翻译： 添加剂制造系统包括支撑体，分配器，用于将金属粉末层输送到支撑体上或支撑体上的下层上，将能量源熔合到金属粉末层的至少一部分，以及定位和配置的磁体 以在熔融层时将磁场施加到金属粉末层的部分。
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公开(公告)号：US07598183B2
公开(公告)日：2009-10-06
申请号：US11533505
申请日：2006-09-20
IPC分类号： H01L21/00
CPC分类号： H01L21/76829 , C23C16/30 , C23C16/45523 , H01L21/02126 , H01L21/022 , H01L21/02216 , H01L21/02274 , H01L21/0234 , H01L21/02348 , H01L21/02351 , H01L21/02362 , H01L21/3122 , H01L21/31633 , H01L21/76835
摘要： A method is provided for processing a substrate surface by delivering a first gas mixture comprising a first organosilicon compound, a first oxidizing gas, and one or more hydrocarbon compounds into a chamber at deposition conditions sufficient to deposit a first low dielectric constant film on the substrate surface. A second gas mixture having a second organosilicon compound and a second oxidizing gas is delivered into the chamber at deposition conditions sufficient to deposit a second low dielectric constant film on the first low dielectric constant film. The flow rate of the second oxidizing gas into the chamber is increased, and the flow rate of the second organosilicon compound into the chamber is decreased to deposit an oxide rich cap on the second low dielectric constant film.
摘要翻译： 提供了一种通过将包含第一有机硅化合物，第一氧化气体和一种或多种烃化合物的第一气体混合物输送到室中的方法来处理衬底表面，该沉积条件足以在衬底上沉积第一低介电常数膜 表面。 具有第二有机硅化合物和第二氧化气体的第二气体混合物在足以在第一低介电常数膜上沉积第二低介电常数膜的沉积条件下被输送到室中。 进入室内的第二氧化气体的流量增加，第二有机硅化合物进入室的流量减少，从而在第二低介电常数膜上沉积氧化物富集盖。
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公开(公告)号：US07547621B2
公开(公告)日：2009-06-16
申请号：US11492316
申请日：2006-07-25
IPC分类号： H01L21/20
CPC分类号： H01L21/32139 , H01L21/02123 , H01L21/02271 , H01L21/02337 , H01L21/31612
摘要： A gate hard mask is deposited on a gate structure using low pressure chemical vapor deposition (LPCVD). By doing so, the wet etch removal ratio (WERR) of the gate hard mask relative to the underlying polysilicon gate layer is increased when compared to prior art hard masks. The LPCVD gate hard mask will not only etch faster than prior art hard masks, but it will also reduce undercutting of the gate oxide. To provide additional control of the wet etch rate, the LPCVD hard mask can be annealed. The annealing can be tailored to achieve the desired etching rate.
摘要翻译： 使用低压化学气相沉积（LPCVD）将栅极硬掩模沉积在栅极结构上。 通过这样做，与现有技术的硬掩模相比，栅极硬掩模相对于下面的多晶硅栅极层的湿蚀刻去除率（WERR）增加。 LPCVD栅极硬掩模将不仅比现有技术的硬掩模蚀刻更快，而且还将减少栅极氧化物的底切。 为了提供对湿蚀刻速率的额外控制，LPCVD硬掩模可被退火。 可以定制退火以实现所需的蚀刻速率。
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25.发明申请公开(公告)号：US20080108210A1
公开(公告)日：2008-05-08
申请号：US11697267
申请日：2007-04-05
IPC分类号： H01L21/425
CPC分类号： H01L21/02115 , C23C14/02 , C23C14/0605 , C23C14/35 , H01L21/02266 , H01L21/02354 , H01L21/2236 , H01L21/26513 , H01L21/268 , H01L21/3146
摘要： A plasma enhanced physical vapor deposition process deposits an amorphous carbon layer on an ion-implanted wafer for use in dynamic surface annealing of the wafer with an intense line beam of a laser wavelength. The deposition process is carried out at a wafer temperature below the dopant clustering threshold temperature, and includes introducing the wafer into a chamber having a carbon-containing target overlying the wafer, and furnishing a carrier gas into the chamber. The process further includes generating a wafer bias voltage and applying target source power to the carbon-containing target sufficient to produce ion bombardment of the carbon-containing target. The wafer bias voltage is set to a level at which the amorphous carbon layer that is deposited has a desired extinction coefficient at the laser wavelength.
摘要翻译： 等离子体增强的物理气相沉积工艺在离子注入晶片上沉积无定形碳层，用于具有激光波长的强线束的晶片的动态表面退火。 沉积工艺在低于掺杂剂聚集阈值温度的晶片温度下进行，并且包括将晶片引入到具有覆盖晶片的含碳靶的腔室中，并将载气提供到腔室中。 该方法还包括产生晶片偏置电压并将目标源功率施加到含碳靶足以产生含碳靶的离子轰击。 将晶片偏置电压设定为在激光波长处具有期望的消光系数的被沉积的无定形碳层的水平。
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公开(公告)号：US06924191B2
公开(公告)日：2005-08-02
申请号：US10463460
申请日：2003-06-16
IPC分类号： H01L21/033 , H01L21/28 , H01L21/311 , H01L21/3213 , H01L21/336 , H01L21/8242
CPC分类号： H01L21/31122 , H01L21/0337 , H01L21/0338 , H01L21/28114 , H01L21/28123 , H01L21/31116 , H01L21/31138 , H01L21/32137 , H01L21/32139 , H01L29/66545 , H01L29/66583
摘要： A method for fabricating features on a substrate having reduced dimensions. The features are formed by defining a first mask on regions of the substrate. The first mask is defined using lithographic techniques. A second mask is then conformably formed on one or more sidewalls of the first mask. The features are formed on the substrate by removing the first mask and then etching the substrate using the second mask as an etch mask.
摘要翻译： 一种在尺寸减小的基板上制造特征的方法。 特征通过在衬底的区域上限定第一掩模而形成。 第一个掩模使用光刻技术定义。 然后在第一掩模的一个或多个侧壁上顺应地形成第二掩模。 通过去除第一掩模在衬底上形成特征，然后使用第二掩模作为蚀刻掩模蚀刻衬底。
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公开(公告)号：US06852647B2
公开(公告)日：2005-02-08
申请号：US10383839
申请日：2003-03-07
IPC分类号： H01L21/314 , H01L21/316 , H01L21/768 , H01L21/31 , H01L21/469
CPC分类号： H01L21/76826 , H01L21/02115 , H01L21/02126 , H01L21/022 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/0234 , H01L21/3105 , H01L21/31122 , H01L21/31144 , H01L21/3146 , H01L21/31633 , H01L21/3212 , H01L21/7681 , H01L21/76828 , H01L21/76829 , H01L21/7684
摘要： A method is provided for processing a substrate including removing amorphous carbon material disposed on a low k dielectric material with minimal or reduced defect formation and minimal dielectric constant change of the low k dielectric material. In one aspect, the invention provides a method for processing a substrate including depositing at least one dielectric layer on a substrate surface, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less, forming amorphous carbon material on the at least one dielectric layer, and removing the one or more amorphous carbon layers by exposing the one or more amorphous carbon layers to a plasma of a hydrogen-containing gas.
摘要翻译： 提供了一种用于处理衬底的方法，包括去除设置在低k电介质材料上的无定形碳材料，具有最小或减少的缺陷形成和低k电介质材料的最小介电常数变化。 在一个方面，本发明提供了一种处理衬底的方法，包括在衬底表面上沉积至少一个电介质层，其中介电层包括硅，氧和碳，并且具有约3或更小的介电常数，形成无定形碳 在所述至少一个电介质层上的材料，以及通过将所述一个或多个非晶碳层暴露于含氢气体的等离子体来去除所述一个或多个非晶碳层。
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公开(公告)号：US06541397B1
公开(公告)日：2003-04-01
申请号：US10112012
申请日：2002-03-29
IPC分类号： H01L2131
CPC分类号： H01L21/76826 , H01L21/02115 , H01L21/02126 , H01L21/022 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/0234 , H01L21/3105 , H01L21/31122 , H01L21/31144 , H01L21/3146 , H01L21/31633 , H01L21/3212 , H01L21/7681 , H01L21/76828 , H01L21/76829 , H01L21/7684
摘要： A method is provided for processing a substrate including removing amorphous carbon material disposed on a low k dielectric material with minimal or reduced defect formation and minimal dielectric constant change of the low k dielectric material. In one aspect, the invention provides a method for processing a substrate including depositing at least one dielectric layer on a substrate surface, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less, forming amorphous carbon material on the at least one dielectric layer, and removing the one or more amorphous carbon layers by exposing the one or more amorphous carbon layers to a plasma of a hydrogen-containing gas.
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公开(公告)号：US08357618B2
公开(公告)日：2013-01-22
申请号：US12257953
申请日：2008-10-24
IPC分类号： H01L21/31
CPC分类号： H01L21/3146 , H01L21/0337 , H01L21/0338
摘要： A method for doubling the frequency of a lithographic process using a photo-resist template mask is described. A device layer having a photo-resist layer formed thereon is first provided. The photo-resist layer is patterned to form a photo-resist template mask. A spacer-forming material layer is deposited over the photo-resist template mask. The spacer-forming material layer is etched to form a spacer mask and to expose the photo-resist template mask. The photo-resist template mask is then removed and an image of the spacer mask is finally transferred to the device layer.
摘要翻译： 描述了使用光致抗蚀剂模板掩模使光刻工艺的频率加倍的方法。 首先提供其上形成有光致抗蚀剂层的器件层。 将光致抗蚀剂层图案化以形成光致抗蚀剂模板掩模。 在光致抗蚀剂模板掩模上沉积间隔物形成材料层。 蚀刻间隔物形成材料层以形成间隔物掩模并露出光刻胶模板掩模。 然后去除光刻胶模板掩模，并且最终将间隔掩模的图像转移到器件层。
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30.发明授权Integral patterning of large features along with array using spacer mask patterning process flow 失效使用间隔物掩模图案化工艺流程的大型特征与阵列的整体图案化公开(公告)号：US07709396B2
公开(公告)日：2010-05-04
申请号：US12234101
申请日：2008-09-19
IPC分类号： H01L21/214 , H01L21/483
CPC分类号： H01L21/3086 , H01L21/3088 , Y10S438/95
摘要： Embodiments of the present invention pertain to methods of forming patterned features on a substrate having an increased density (i.e. reduced pitch) as compared to what is possible using standard photolithography processing techniques using a single high-resolution photomask while also allowing both the width of the patterned features and spacing (trench width) between the patterned features to vary within an integrated circuit.
摘要翻译： 本发明的实施例涉及在使用单个高分辨率光掩模的标准光刻处理技术的情况下与具有增加的密度（即减小的间距）的衬底上形成图案化特征的方法，同时还允许 图案化特征和图案化特征之间的间隔（沟槽宽度）在集成电路内变化。
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