公开(公告)号：US20160267046A1

公开(公告)日：2016-09-15

申请号：US15064964

申请日：2016-03-09

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris ,  Igor Wojewoda ,  Alex Dumais ,  Mike Catherwood ,  Brian Fall ,  Jason Tollefson ,  Calum Wilke ,  Dave Mickey ,  Thomas Spohrer

IPC: G06F13/42 ,  G06F13/16 ,  G06F13/364

CPC classification number: G06F13/4282 ,  G06F13/1673 ,  G06F13/364 ,  G06F13/385 ,  G06F15/7807 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A microcontroller device has a housing with a plurality of external pins having a plurality of input/output pins, a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, and a pad ownership multiplexer unit being controllable to assign control of the input/output pins to either the first microcontroller or the second microcontroller, wherein the number of external pins is less than the sum of a data buswidth of the first and second microcontroller.

Abstract translation: 微控制器装置具有壳体，多个外部引脚具有多个输入/输出引脚，具有第一中央处理单元（CPU）的第一微控制器，与第一CPU耦合的第一系统总线，与第一中央处理单元 系统总线和与第一系统总线耦合的第一多个外围设备，具有第二中央处理单元（CPU）的第二微控制器，与第二CPU耦合的第二系统总线，与第二系统总线耦合的第二存储器，以及 与第二系统总线耦合的第二多个外围设备，以及焊盘所有权复用器单元，其可控制以将输入/输出引脚的控制分配给第一微控制器或第二微控制器，其中外部引脚的数量小于 第一和第二微控制器的数据总线宽度之和。

公开(公告)号：US09356613B1

公开(公告)日：2016-05-31

申请号：US14538036

申请日：2014-11-11

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris

IPC: H03M1/66 ,  H03M1/06 ,  H03K4/06

CPC classification number: H03K4/06 ,  G06F1/022 ,  H03K7/08 ,  H03M1/0631 ,  H03M1/825

Abstract: A phase accumulator style circuit generates an output stream of pulses. The density of the pulse stream is proportional to the input data value relative to the maximum value supported by the bit width of an adder. The output pulse density is representative of the desired output voltage. The pulse stream may be filtered with a resistor-capacitor (RC) low pass filter to yield an analog voltage. Faster clock rates support the use of smaller output filters that reduce circuit cost. This circuit provides triangle wave generation wherein the DAC output ramps up and down at a user specified rate (slope) between user specified maximum and minimum amplitude values. The up and down triangle wave ramp rates (up and down slopes) may be different and independent or the same.

Abstract translation: 相位累加器式电路产生输出脉冲流。 脉冲流的密度与输入数据值相对于由加法器的位宽度支持的最大值成比例。 输出脉冲密度代表所需的输出电压。 可以用电阻 - 电容（RC）低通滤波器对脉冲流进行滤波，以产生模拟电压。 更快的时钟速率支持使用更小的输出滤波器，降低电路成本。 该电路提供三角波生成，其中DAC输出以用户指定的最大和最小振幅值之间的用户指定速率（斜率）上下翻转。 上下三角波斜坡速率（上下斜坡）可能是不同的和独立的或相同的。

公开(公告)号：US20160134263A1

公开(公告)日：2016-05-12

申请号：US14538068

申请日：2014-11-11

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris

IPC: H03K3/017 ,  H03K3/0233

CPC classification number: H03K3/02337 ,  G05B11/16 ,  H02M2001/0003

Abstract: An asymmetric hysteretic controller comprises an analog comparator coupled with a fast slew rate DAC, or a digital comparator coupled with an ADC plus some digital control logic. The comparator, analog or digital, operates as a sequential windowed comparator having high and low limits. The sense parameter is compared to a high or a low limit and when the sense parameter reaches the selected high or low limit, the controlled device is turned off or on, respectively. When the hysteretic controller state comparison reversal occurs: (a) the comparator output may be blanked by the control logic, (b) the comparator polarity may be reversed by the control logic, (c) the control logic may command the other process limit to be selected for comparison with the sense parameter, and (d) then the comparator output may be re-enabled.

Abstract translation: 非对称滞后控制器包括与快速压摆率DAC耦合的模拟比较器，或与ADC加上一些数字控制逻辑的数字比较器。 比较器，模拟或数字，作为具有高限和低限的顺序窗口比较器。 将感测参数与高限或下限进行比较，并且当感测参数达到选定的上限或下限时，受控装置分别关闭或接通。 当迟滞控制器状态比较反转发生时：（a）比较器输出可能被控制逻辑消隐，（b）比较器极性可能由控制逻辑反转，（c）控制逻辑可以命令另一个过程限制 被选择用于与感测参数进行比较，和（d）然后可以重新使能比较器输出。

公开(公告)号：US09337811B1

公开(公告)日：2016-05-10

申请号：US14538068

申请日：2014-11-11

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris

IPC: H03K3/017 ,  H03K3/0233

CPC classification number: H03K3/02337 ,  G05B11/16 ,  H02M2001/0003

Abstract: An asymmetric hysteretic controller comprises an analog comparator coupled with a fast slew rate DAC, or a digital comparator coupled with an ADC plus some digital control logic. The comparator, analog or digital, operates as a sequential windowed comparator having high and low limits. The sense parameter is compared to a high or a low limit and when the sense parameter reaches the selected high or low limit, the controlled device is turned off or on, respectively. When the hysteretic controller state comparison reversal occurs: (a) the comparator output may be blanked by the control logic, (b) the comparator polarity may be reversed by the control logic, (c) the control logic may command the other process limit to be selected for comparison with the sense parameter, and (d) then the comparator output may be re-enabled.

Abstract translation: 非对称滞后控制器包括与快速压摆率DAC耦合的模拟比较器，或与ADC加上一些数字控制逻辑的数字比较器。 比较器，模拟或数字，作为具有高限和低限的顺序窗口比较器。 将感测参数与高限或下限进行比较，并且当感测参数达到选定的上限或下限时，受控装置分别关闭或接通。 当迟滞控制器状态比较反转发生时：（a）比较器输出可能被控制逻辑消隐，（b）比较器极性可能由控制逻辑反转，（c）控制逻辑可以命令另一个过程限制 被选择用于与感测参数进行比较，和（d）然后可以重新使能比较器输出。

公开(公告)号：US10795783B2

公开(公告)日：2020-10-06

申请号：US16158471

申请日：2018-10-12

Applicant: Microchip Technology Incorporated

Inventor： Igor Wojewoda ,  Bryan Kris ,  Stephen Bowling ,  Yong Yuenyongsgool

IPC: G06F11/00 ,  G06F11/16 ,  G06F11/14 ,  H03K5/19

Abstract: A clock monitor includes a test clock input, as a reference clock input, another clock input, a measurement circuit, and control logic. The measurement circuit generates a measurement of a frequency or a duty cycle of the test clock input using the reference clock input, which is compared to a threshold. The control logic determines whether the measurement exceeded the threshold and, based on the measurement exceeding the threshold, cause generation of another measurement of a frequency or a duty cycle using the third clock input in combination with the first clock input or the reference clock input. The control logic may determine whether the other measurement exceeded a threshold and, based on such a determination, further determine that the test clock input or the reference clock input are faulty.

公开(公告)号：US20190114235A1

公开(公告)日：2019-04-18

申请号：US16158471

申请日：2018-10-12

Applicant: Microchip Technology Incorporated

Inventor： Igor Wojewoda ,  Bryan Kris ,  Stephen Bowling ,  Yong Yuenyongsgool

IPC: G06F11/16 ,  G06F11/34 ,  G06F11/14

Abstract: A clock monitor includes a test clock input, as a reference clock input, another clock input, a measurement circuit, and control logic. The measurement circuit generates a measurement of a frequency or a duty cycle of the test clock input using the reference clock input, which is compared to a threshold. The control logic determines whether the measurement exceeded the threshold and, based on the measurement exceeding the threshold, cause generation of another measurement of a frequency or a duty cycle using the third clock input in combination with the first clock input or the reference clock input. The control logic may determine whether the other measurement exceeded a threshold and, based on such a determination, further determine that the test clock input or the reference clock input are faulty.

公开(公告)号：US10193514B2

公开(公告)日：2019-01-29

申请号：US15723142

申请日：2017-10-02

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris ,  James E. Bartling

IPC: H03F1/34 ,  H03G1/00 ,  H03F3/45 ,  H03G3/00

Abstract: An integrated circuit amplifier configurable to be either a programmable gain amplifier or an operational amplifier comprises two output blocks, one output block is optimized for programmable gain amplifier operation, and the other output block is optimized for operational amplifier applications. A common single input stage, input offset calibration and bias generation circuits are used with either amplifier configuration. Thus duplication of the input stage, offset calibration and bias generation circuits are eliminated while still selectably providing for either a programmable gain amplifier or operational amplifier configuration.

公开(公告)号：US10122375B2

公开(公告)日：2018-11-06

申请号：US15915796

申请日：2018-03-08

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris ,  Neil Deutscher ,  Thomas S. Spohrer

IPC: H03M1/34 ,  H03K5/131 ,  H03K5/14 ,  H03M1/10 ,  H03M1/38 ,  H03M1/00 ,  H03M1/18 ,  H03K5/00 ,  H03M1/50

Abstract: Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.

公开(公告)号：US10090850B2

公开(公告)日：2018-10-02

申请号：US15484965

申请日：2017-04-11

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris ,  Neil Deutscher

IPC: H03M1/12 ,  H03M1/34 ,  H03M1/10 ,  H03K5/131 ,  H03K5/14

Abstract: Embodiments of the present disclosure include a microcontroller with a processor, memory, and peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines, a circuit including a set of delay elements included in the differential digital delay lines, and another circuit including another set of delay elements included in the differential digital delay lines. The first circuit is configured to generate data representing an analog to digital conversion of an input. The second circuit is configured to calibrate a source to the differential digital delay lines.

公开(公告)号：US20180226984A1

公开(公告)日：2018-08-09

申请号：US15949479

申请日：2018-04-10

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris ,  Neil Deutscher

IPC: H03M1/34 ,  H03K5/131 ,  H03K5/14 ,  H03M1/10

CPC classification number: H03M1/34 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/00058 ,  H03M1/007 ,  H03M1/1009 ,  H03M1/1028 ,  H03M1/1057 ,  H03M1/1071 ,  H03M1/18 ,  H03M1/38 ,  H03M1/502

Abstract: Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines, a circuit including a set of delay elements included in the differential digital delay lines, and another circuit including another set of delay elements included in the differential digital delay lines. The first circuit is configured to generate data representing an analog to digital conversion of an input. The second circuit is configured to calibrate a source to the differential digital delay lines.