公开(公告)号：US20180137921A1

公开(公告)日：2018-05-17

申请号：US15869501

申请日：2018-01-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Benjamin Louie ,  Ali Mohammadzadeh ,  Aaron S. Yip

IPC: G11C16/24 ,  G11C16/26 ,  G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  G11C16/06 ,  G11C16/10

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: Memory devices including an array of memory cells, a plurality of access lines selectively coupled to respective pluralities of memory cells of the array of memory cells, a plurality of first registers, a second register, a first multiplexer, a second multiplexer, and a decoder configured to selectively connect a corresponding access line to a selected voltage source of a plurality of voltage sources in response to the output of the second multiplexer, wherein the second multiplexer is configured to pass a selected one of the output of the second register and the output of the first multiplexer to its output, and wherein the first multiplexer is configured to pass a selected one of the outputs of the plurality of first registers to its output.

公开(公告)号：US20150279432A1

公开(公告)日：2015-10-01

申请号：US14735350

申请日：2015-06-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip ,  Mark A. Helm ,  Ramin Ghodsi

IPC: G11C5/02 ,  G11C5/06

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C8/08 ,  G11C11/06035 ,  G11C11/06064 ,  G11C11/063 ,  G11C16/02 ,  G11C16/0483 ,  H01L27/11531 ,  H01L27/11573 ,  Y10T29/49069

Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.

Abstract translation: 在一个实施例中，存储器设备包括层级的存储器单元的堆叠，位于存储器单元的层级之上的层级的本地设备层，以及与本地设备层基本相同的级别的全球设备层 。 本地设备可以提供对数据线的选择性访问。 全局设备可以提供对全局接入线的选择性访问。 一层存储器单元可以由全球设备层的全局设备选择性地耦合到全局接入线路。

公开(公告)号：US20240413145A1

公开(公告)日：2024-12-12

申请号：US18808990

申请日：2024-08-19

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip ,  Kunal R. Parekh ,  Akira Goda

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises a first control logic region comprising a first control logic device including at least a word line driver. The microelectronic device further comprises a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20240386965A1

公开(公告)日：2024-11-21

申请号：US18787957

申请日：2024-07-29

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34

Abstract: Control logic in a memory device receives a request to program data to a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and identifies a first sub-block of the plurality of sub-blocks to be programmed with at least a portion of the data. The control logic further causes a plurality of control signals to be applied to a plurality of logical select gate layers positioned at a drain-side of the block to activate the first sub-block, and causes a program signal to be applied to a selected wordline of the block to program at least the portion of the data to a memory cell in the first sub-block and associated with the selected wordline.

公开(公告)号：US20240315028A1

公开(公告)日：2024-09-19

申请号：US18604200

申请日：2024-03-13

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Aaron S. Yip ,  Giovanni Mazzone ,  Matthew King

IPC: H10B43/27 ,  G11C16/04 ,  G11C16/10 ,  H10B41/27

CPC classification number: H10B43/27 ,  G11C16/0483 ,  G11C16/10 ,  H10B41/27

Abstract: A system for manufacturing a memory device forms a memory array comprising a plurality of memory cells arranged in a plurality of memory strings along a plurality of memory array pillars, wherein respective subsets of the memory array pillars correspond to respective sub-blocks of a block of the memory array, and forms a plurality of deintegrated source segments adjacent to the memory array, wherein the source segments of the plurality of deintegrated source segments are associated with respective sub-blocks and are physically segregated from one another.

公开(公告)号：US20240071501A1

公开(公告)日：2024-02-29

申请号：US18364397

申请日：2023-08-02

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Umberto Maria Meotto ,  Aaron S. Yip

IPC: G11C16/04 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Microelectronic devices include a stack having a vertically alternating sequence of insulative and conductive structures arranged in tiers. Slit structures extend through the stack, dividing the stack into blocks. A first series of stadiums—within the stack of a first block of a pair of the blocks—includes at least one stadium having multiple parallel sets of staircases. A second series of stadiums—within the stack of a second block of the pair of blocks—includes at least one additional stadium having additional multiple parallel sets of staircases that are mirrored, across one of the slit structures, to the multiple parallel sets of staircases of the first series. In methods of fabrication, common mask openings are used to form the mirrored staircase profiles once stadiums are already at substantially their final depths in the stack structure. Electronic systems are also disclosed.

公开(公告)号：US20230112381A1

公开(公告)日：2023-04-13

申请号：US17944940

申请日：2022-09-14

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08

Abstract: Control logic in a memory device receives a request to program data to a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and identifies a first sub-block of the plurality of sub-blocks to be programmed with at least a portion of the data. The control logic further causes a plurality of control signals to be applied to a plurality of logical select gate layers positioned at a drain-side of the block to activate the first sub-block, and causes a program signal to be applied to a selected wordline of the block to program at least the portion of the data to a memory cell in the first sub-block and associated with the selected wordline.

公开(公告)号：US11587919B2

公开(公告)日：2023-02-21

申请号：US16932098

申请日：2020-07-17

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip ,  Kunal R. Parekh ,  Akira Goda

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises first control logic region comprising a first control logic devices including at least a word line driver. The microelectronic device further comprise a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US11335700B2

公开(公告)日：2022-05-17

申请号：US17208868

申请日：2021-03-22

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip

IPC: G11C8/10 ,  G11C16/26 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  G11C16/08 ,  G11C11/56 ,  H01L21/768 ,  H01L21/3213 ,  G11C16/24

Abstract: A memory device stores data in non-volatile memory. The memory device includes a non-volatile memory array. The memory array includes tiers for accessing data stored in blocks of the memory array, including a block having a left block portion and a right block portion. A first staircase is positioned between the left block portion and the right block portion, and a bottom portion of the first staircase includes steps corresponding to first tiers of the left block portion. A second staircase is positioned between the left block portion and the right block portion, and a top portion of the second staircase includes steps corresponding to second tiers of the right block portion. The steps of the first staircase and the steps of the second staircase descend in opposite directions.

公开(公告)号：US20220076751A1

公开(公告)日：2022-03-10

申请号：US16948236

申请日：2020-09-09

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip ,  Tomoko Ogura Iwasaki

IPC: G11C16/08 ,  G11C16/04

Abstract: A memory device comprises a substrate and a memory array disposed above the substrate, the memory array comprising a plurality of vertically stacked layers, each vertically stacked layer comprising a plurality of word lines. The memory device further comprises a plurality of vertical string driver circuits disposed above the memory array, wherein each of the plurality of vertical string driver circuits comprises one or more semiconductor devices coupled to a respective one of the plurality of word lines.