公开(公告)号：US20250079405A1

公开(公告)日：2025-03-06

申请号：US18951102

申请日：2024-11-18

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Seng Kim Ye ,  Chin Hui Chong

IPC: H01L25/065 ,  H01L25/00

Abstract: Semiconductor devices having three-dimensional bonding schemes and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device includes a package substrate, a stack of semiconductor dies carried by the package substrate, and an interconnect module carried by the package substrate adjacent the stack of semiconductor dies. The stack of semiconductor dies can include a first die carried by the package substrate and a second die carried by the first die. Meanwhile, the interconnect module can include at least a first tier and a second tier. The first tier can be carried by and electrically coupled to the package substrate, and the second tier can be carried by and electrically coupled to the first tier. In turn, the second die can be electrically coupled to the second tier.

公开(公告)号：US12243807B2

公开(公告)日：2025-03-04

申请号：US18398120

申请日：2023-12-27

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Chin Hui Chong ,  Hem P. Takiar ,  Seng Kim Ye ,  Kelvin Tan Aik Boo

IPC: H01L29/76 ,  H01L23/48 ,  H01L23/498 ,  H01L27/08 ,  H01L29/00 ,  H01L49/02

Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.

公开(公告)号：US20240404995A1

公开(公告)日：2024-12-05

申请号：US18646688

申请日：2024-04-25

Applicant: Micron Technology, Inc.

Inventor： Chin Hui Chong ,  Hong Wan Ng ,  See Hiong Leow ,  Ling Pan ,  Seng Kim Ye ,  Kelvin Tan Aik Boo

IPC: H01L25/065 ,  H01L25/00 ,  H05K1/02 ,  H10B80/00

Abstract: An apparatus includes selectable a circuit placement mechanism configured to support two or more different circuit layouts. The circuit placement mechanism may include an overlap of electrical connections associated with the two or more circuit layouts and joined through an etch back selector. The etch back selector may enable the apparatus to function according to a selected one of the two or more different circuit layouts.

公开(公告)号：US20240292522A1

公开(公告)日：2024-08-29

申请号：US18424681

申请日：2024-01-26

Applicant: Micron Technology, Inc.

Inventor： Prasad Nagavenkata Nune ,  Christopher Glancey ,  Yeow Chon Ong ,  Hong Wan Ng

IPC: H05K1/02

CPC classification number: H05K1/0271 ,  H05K2201/09418 ,  H05K2201/10159

Abstract: A microelectronic device package assembly includes a package board and a stiffener device attached to the package board. The package board has a first side and a second side. The stiffener device includes an upper stiffener, a lower stiffener, and one or more damper device. The upper stiffener is above the first side of the package board and has a die side and a package side. The lower stiffener is interposed between the upper stiffener and the package board and has a damper side and a board side. The lower stiffener includes through-package anchors extending from the board side and through the package board. The one or more damper devices are interposed between and are in contact with each of the upper stiffener and the lower stiffener. Microelectronic devices and electronic systems are also described.

公开(公告)号：US20240274583A1

公开(公告)日：2024-08-15

申请号：US18514107

申请日：2023-11-20

Applicant: Micron Technology, Inc.

Inventor： Seng Kim Ye ,  Hong Wan Ng

IPC: H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L21/78 ,  H01L24/32 ,  H01L24/33 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/18 ,  H01L25/50 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8314 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2224/8592 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/1205 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/207

Abstract: Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a support member attached to the package substrate. The support member can be separated from the first semiconductor die, and a second semiconductor die can have one region coupled to the support member and another region coupled to the first semiconductor die.

公开(公告)号：US20240234403A1

公开(公告)日：2024-07-11

申请号：US18545996

申请日：2023-12-19

Applicant: Micron Technology, Inc.

Inventor： Seng Kim Dalson Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng ,  See Hiong Leow ,  Ling Pan

IPC: H01L25/18 ,  H01L21/48 ,  H01L23/498 ,  H01L25/00 ,  H10B80/00

CPC classification number: H01L25/18 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L25/50 ,  H10B80/00 ,  H01L24/48

Abstract: A microelectronic device package includes a microelectronic device coupled to a substrate. The microelectronic device package further includes a stack of semiconductor dies positioned over the microelectronic device. The microelectronic device package also includes an interposer positioned between the microelectronic device and the stack of semiconductor dies. The interposer includes a conductive structure electrically connecting the microelectronic device and a ground circuit of the substrate. The interposer further includes an insulative structure positioned between the conductive structure and the stack of semiconductor dies.

公开(公告)号：US20240203963A1

公开(公告)日：2024-06-20

申请号：US18588595

申请日：2024-02-27

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Kelvin Tan Aik Boo ,  Chin Hui Chong ,  Hem P. Takiar ,  Seng Kim Ye

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/16 ,  H01L21/563 ,  H01L23/3192 ,  H01L25/0657 ,  H01L25/50 ,  H01L28/40

Abstract: Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device is an assembly that includes a package substrate having a front side and a backside opposite the front side. A controller die with a first longitudinal footprint can be attached to the front side of the package substrate. A passive electrical component is also attached to the front side of the package substrate. A stack of semiconductor dies can be attached to the controller die and the passive electrical component. The stack of semiconductor dies has a second longitudinal footprint greater than the first longitudinal footprint in at least one dimension. The controller die and the passive electrical component are positioned at least partially within the second longitudinal footprint, thereby at least partially supporting the stack of semiconductor dies.

公开(公告)号：US20240194547A1

公开(公告)日：2024-06-13

申请号：US18517980

申请日：2023-11-22

Applicant: Micron Technology, Inc.

Inventor： Ling Pan ,  Seng Kim Ye ,  Hong Wan Ng ,  Kelvin Aik Boo Tan ,  See Hiong Leow

IPC: H01L23/13 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/13 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/48 ,  H01L25/18 ,  H10B80/00 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265

Abstract: A variety of applications can include systems having packaged electronic devices. One or more of the packaged electronic devices can include a package substrate, having a first section and a second section with the second section elevated with respect to the first section, to support dies in the two sections. The first section can have a first top surface and a bottom surface with one or more layers of material between the first top surface and the bottom surface. The second section can include a second top surface and the bottom surface of the first section with the one or more layers of material of the first section extending horizontally from the first section. The second section can have one or more additional layers of material between the second top surface and the one or more layers of material of the first section extending horizontally from the first section.

公开(公告)号：US20240128163A1

公开(公告)日：2024-04-18

申请号：US18398120

申请日：2023-12-27

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Chin Hui Chong ,  Hem P. Takiar ,  Seng Kim Ye ,  Kelvin Tan Aik Boo

IPC: H01L23/48 ,  H01L23/498 ,  H01L27/08

CPC classification number: H01L23/481 ,  H01L23/49816 ,  H01L27/0805 ,  H01L28/40

Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.

公开(公告)号：US11942460B2

公开(公告)日：2024-03-26

申请号：US17137085

申请日：2020-12-29

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Kelvin Tan Aik Boo ,  Chin Hui Chong ,  Hem P. Takiar ,  Seng Kim Ye

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L25/16 ,  H01L49/02

CPC classification number: H01L25/16 ,  H01L21/563 ,  H01L23/3192 ,  H01L25/0657 ,  H01L25/50 ,  H01L28/40

Abstract: Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device is an assembly that includes a package substrate having a front side and a backside opposite the front side. A controller die with a first longitudinal footprint can be attached to the front side of the package substrate. A passive electrical component is also attached to the front side of the package substrate. A stack of semiconductor dies can be attached to the controller die and the passive electrical component. The stack of semiconductor dies has a second longitudinal footprint greater than the first longitudinal footprint in at least one dimension. The controller die and the passive electrical component are positioned at least partially within the second longitudinal footprint, thereby at least partially supporting the stack of semiconductor dies.