公开(公告)号：US20160247747A1

公开(公告)日：2016-08-25

申请号：US15144065

申请日：2016-05-02

Applicant: Micron Technology, Inc.

Inventor： Jeffery W. Janzen ,  Michael Chaine ,  Kyle K. Kirby ,  William M. Hiatt

IPC: H01L23/48 ,  H01L25/00 ,  H01L23/525 ,  H01L27/02 ,  H01L23/00 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/50 ,  H01L21/76898 ,  H01L21/82 ,  H01L23/52 ,  H01L23/525 ,  H01L23/60 ,  H01L23/62 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0248 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/13034 ,  H01L2924/00014

Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.

公开(公告)号：US09305865B2

公开(公告)日：2016-04-05

申请号：US14068837

申请日：2013-10-31

Applicant: Micron Technology, Inc.

Inventor： Anurag Jindal ,  Jian He ,  Lalapet Rangan Vasudevan ,  Kyle K. Kirby ,  Hongqi Li

IPC: H01L21/00 ,  H01L21/76 ,  H01L23/48 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/481 ,  H01L21/76801 ,  H01L21/76838 ,  H01L21/76898 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of manufacturing semiconductor devices and semiconductor devices with through-substrate vias (TSVs). One embodiment of a method of manufacturing a semiconductor device includes forming an opening through a dielectric structure and at least a portion of a semiconductor substrate, and forming a dielectric liner material having a first portion lining the opening and a second portion on an outer surface of the dielectric structure laterally outside of the opening. The method further includes removing the conductive material such that the second portion of the dielectric liner material is exposed, and forming a damascene conductive line in the second portion of the dielectric liner material that is electrically coupled to the TSV.

Abstract translation: 制造具有贯通衬底通孔（TSV）的半导体器件和半导体器件的方法。 制造半导体器件的方法的一个实施例包括通过电介质结构和半导体衬底的至少一部分形成开口，以及形成具有衬在开口上的第一部分的电介质衬垫材料和在外表面上的第二部分 电介质结构横向于开口外侧。 该方法还包括去除导电材料，使得电介质衬垫材料的第二部分被暴露，并且在电耦合到TSV的电介质衬垫材料的第二部分中形成镶嵌导电线。

公开(公告)号：US20150115445A1

公开(公告)日：2015-04-30

申请号：US14068837

申请日：2013-10-31

Applicant: Micron Technology, Inc.

Inventor： Anurag Jindal ,  Jian He ,  Lalapet Rangan Vasudevan ,  Kyle K. Kirby ,  Hongqi Li

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76801 ,  H01L21/76838 ,  H01L21/76898 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of manufacturing semiconductor devices and semiconductor devices with through-substrate vias (TSVs). One embodiment of a method of manufacturing a semiconductor device includes forming an opening through a dielectric structure and at least a portion of a semiconductor substrate, and forming a dielectric liner material having a first portion lining the opening and a second portion on an outer surface of the dielectric structure laterally outside of the opening. The method further includes removing the conductive material such that the second portion of the dielectric liner material is exposed, and forming a damascene conductive line in the second portion of the dielectric liner material that is electrically coupled to the TSV.

Abstract translation: 制造具有贯通衬底通孔（TSV）的半导体器件和半导体器件的方法。 制造半导体器件的方法的一个实施例包括通过电介质结构和半导体衬底的至少一部分形成开口，以及形成具有衬在开口上的第一部分的电介质衬垫材料和在外表面上的第二部分 电介质结构横向于开口外侧。 该方法还包括去除导电材料，使得电介质衬垫材料的第二部分被暴露，并且在电耦合到TSV的电介质衬垫材料的第二部分中形成镶嵌导电线。

公开(公告)号：US20150093892A1

公开(公告)日：2015-04-02

申请号：US14563953

申请日：2014-12-08

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh ,  Sarah A. Niroumand

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/306

Abstract: Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.

Abstract translation: 本文公开了具有贯穿衬底互连和相关制造方法的微电子器件。 在一个实施例中，半导体器件包括承载第一和第二金属化层的半导体衬底。 第二金属化层与半导体衬底间隔开，其间具有第一金属化层。 半导体器件还包括至少部分延伸穿过半导体衬底的导电互连。 第一金属化层经由第二金属化层与导电互连电接触。

公开(公告)号：US08929052B2

公开(公告)日：2015-01-06

申请号：US13921022

申请日：2013-06-18

Applicant: Micron Technology, Inc.

Inventor： Dewali Ray ,  Warren M. Farnworth ,  Kyle K. Kirby

IPC: H01L21/683

CPC classification number: H01L21/6833

Abstract: A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to electrostatically bond a substrate to the electrostatic carrier. The conductor is removed from physically contacting the exposed conductive electrode. Dielectric material is applied over the conductive electrode. The substrate is treated while it is electrostatically bonded to the electrostatic carrier. In one embodiment, a conductor is forced through dielectric material that is received over a conductive electrode of an electrostatic carrier to physically contact the conductor with the conductive electrode to electrostatically bond a substrate to the electrostatic carrier. After removing the conductor from the dielectric material, the substrate is treated while it is electrostatically bonded to the electrostatic carrier. Electrostatic carriers for retaining substrates for processing, and such assemblies, are also disclosed.

Abstract translation: 处理衬底的方法包括使静电载体的暴露的导电电极与导体物理接触，以将衬底静电结合到静电载体上。 导体从物理接触暴露的导电电极去除。 电介质材料施加在导电电极上。 在静电接触静电载体的同时对衬底进行处理。 在一个实施例中，将导体强制通过电介质材料，该电介质材料被接纳在静电载体的导电电极上，以使导体与导电电极物理接触以将基底静电地接合到静电载体上。 在从电介质材料中去除导体之后，将衬底静电结合到静电载体上进行处理。 还公开了用于保持用于加工的基材和这种组件的静电载体。

公开(公告)号：US20140287584A1

公开(公告)日：2014-09-25

申请号：US14144806

申请日：2013-12-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh ,  Philip J. Ireland ,  Sarah A. Niroumand

IPC: H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/02063 ,  H01L21/76843 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L2224/13025 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

Abstract: Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material.

Abstract translation: 具有通硅通孔的微电子器件及其相关制造方法。 一种用于形成钨硅通孔的方法的一个实施例，包括形成具有侧壁的开口，使得所述开口延伸穿过已经形成有微电子结构的衬底的至少一部分。 该方法可以进一步包括用介电材料衬里侧壁，在介电材料上沉积钨，使得空腔延伸穿过钨的至少一部分，并用多晶硅材料填充空腔。

公开(公告)号：US20130295766A1

公开(公告)日：2013-11-07

申请号：US13940034

申请日：2013-07-11

Applicant: Micron Technology, Inc.

Inventor： Salman Akram ,  Charles M. Watkins ,  William M. Hiatt ,  David R. Hembree ,  James M. Wark ,  Warren M. Farnworth ,  Mark E. Tuttle ,  Sidney B. Rigg ,  Steven D. Oliver ,  Kyle K. Kirby ,  Alan G. Wood ,  Lu Velicky

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/45 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract translation: 公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。 此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。

公开(公告)号：US20240332229A1

公开(公告)日：2024-10-03

申请号：US18619071

申请日：2024-03-27

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Tzu Ching Hung ,  Kyle K. Kirby ,  Julia VanWinkle ,  Kyle B. Campbell ,  Bret K. Street

IPC: H01L23/00 ,  H01L21/66

CPC classification number: H01L24/06 ,  H01L22/32 ,  H01L24/03 ,  H01L24/08 ,  H01L2224/06517 ,  H01L2224/08146

Abstract: A semiconductor device is provided. The semiconductor device can have a front side at which circuitry is disposed. The circuitry can include a pad and a plurality of lines. A first layer of dielectric material can be disposed at the front side at least partially over the pad and the plurality of lines. A second layer of dielectric material can be disposed at the front side at least partially over the first layer of dielectric material. A dual damascene pad can extend through the first layer of dielectric material and the second layer of dielectric material to the pad. A dummy pad can be disposed in the second layer of dielectric material above the plurality of lines and spaced from the dual damascene pad. In doing so, a reliable semiconductor device can be implemented.

公开(公告)号：US11978656B2

公开(公告)日：2024-05-07

申请号：US16983559

申请日：2020-08-03

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L21/74 ,  H01L21/265 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/498 ,  H01L29/66 ,  H01L29/78 ,  H10B12/00 ,  H01L27/06

CPC classification number: H01L21/743 ,  H01L21/26513 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/49816 ,  H01L29/66568 ,  H01L29/78 ,  H10B12/485 ,  H01L27/0694 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H10B12/09

Abstract: Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

公开(公告)号：US20240087987A1

公开(公告)日：2024-03-14

申请号：US18507721

申请日：2023-11-13

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76877 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Systems and methods for a semiconductor device having a front-end-of-line structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor substrate material and a front side, and an interconnect structure extending through the dielectric material. The interconnect structure may be electrically connected to a semiconductor memory array proximate the front side of the dielectric material. The semiconductor device may further have an insulating material encasing at least a portion of the semiconductor memory array and an opening created during back-end-of-line processing through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.