公开(公告)号：US20200265879A1

公开(公告)日：2020-08-20

申请号：US16276481

申请日：2019-02-14

Applicant: Micron Technology, Inc.

Inventor： Hiroyuki Matsuno ,  Shuichi Tsukada

IPC: G11C7/10 ,  G11C11/4091 ,  G11C11/4072 ,  G11C11/4074 ,  G11C7/22 ,  G11C7/06 ,  G11C8/18

Abstract: Apparatuses including input buffers and methods for operating input buffers are described. An example input buffer includes a plurality of input buffer circuits, each receiving input data and activated by a respective clock signal. An input buffer circuit includes a decision feedback equalizer (DFE) having adjustable capacitances and reference capacitances to set a reference level of the input buffer circuit. The capacitance of the adjustable capacitances may be set by a code. The DFE provides a capacitance of the adjustable capacitances to a first sense node and further provides a capacitance of the reference capacitances to a second sense node to set the reference level of the input buffer circuit. The input buffer circuit provides output data based on the input data and the reference level set by the DFE.

公开(公告)号：US20190173470A1

公开(公告)日：2019-06-06

申请号：US16273547

申请日：2019-02-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hiroyuki Matsuno ,  Shuichi Tsukada

IPC: H03K19/00 ,  H03K19/0185 ,  G11C8/10 ,  G11C7/10 ,  G11C5/14 ,  G11C7/22 ,  G11C14/00

Abstract: An example apparatus according to an embodiment of the disclosure includes first and second voltage terminals, and first, second, and third circuit nodes. A potential of the first circuit node is changed based on an input signal. A flip-flop circuit includes first and second inverters cross-coupled to each other. The first inverter is coupled between the first voltage terminal and the second circuit node. A first transistor is coupled between the second and third circuit nodes, and the first transistor has a control electrode coupled to the first circuit node. A first current control circuit is coupled between the third circuit node and the second voltage terminal, and an amount of current flowing through the first current control circuit being controlled based on a first code signal.

公开(公告)号：US20190115055A1

公开(公告)日：2019-04-18

申请号：US16229214

申请日：2018-12-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shuichi Tsukada

IPC: G11C7/10 ,  G11C5/14 ,  G11C11/4093 ,  G11C7/06

CPC classification number: G11C7/1084 ,  G11C5/14 ,  G11C7/02 ,  G11C7/065 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/4074 ,  G11C11/4093

Abstract: Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes: a first amplifier that provides first and second intermediate voltages responsive to first and second input voltages; first and second voltage terminals; a circuit node; a first transistor coupled between the first voltage terminal and the circuit node and is turned on responsive to at least one of the first and second intermediate voltages; a second amplifier including first and second inverters, at least one of the first and second inverters being coupled between the circuit node and the second voltage terminal; and first and second output nodes, the first output node being coupled to an input node of the first inverter and an output node of the second inverter, and the second output node being coupled to an output node of the first inverter and an input node of the second inverter.

公开(公告)号：US10199081B1

公开(公告)日：2019-02-05

申请号：US15833688

申请日：2017-12-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenji Asaki ,  Shuichi Tsukada

IPC: H03B1/00 ,  G11C7/12 ,  H03K17/687

Abstract: Apparatuses and methods for providing bias signals in a semiconductor device are described. As example apparatus includes a power supply line configured to provide a supply voltage and further includes first and second nodes. An impedance element is coupled between the power supply line and the first node and a first transistor having a gate, a source coupled to the first node, and a drain coupled to the second node. A reference line is configured to provide a reference voltage. A second transistor has a gate, a source coupled to the reference line, and a drain. The gate and the drain of the second transistor are coupled to the gate of the first transistor.

公开(公告)号：US09286977B2

公开(公告)日：2016-03-15

申请号：US14473489

申请日：2014-08-29

Applicant: Micron Technology, Inc.

Inventor： Shuichi Tsukada

IPC: G11C11/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: G11C13/004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/79 ,  H01L27/24

Abstract: A semiconductor device including: a resistive memory element; a data line electrically coupled to the resistive memory element; a control line; a power supply line; and a control circuit including a first constant current element, a first transistor, and a second transistor. In the control circuit, the first transistor has a gate coupled to the data line, one of a source and a drain coupled to the first constant current element, and the other one of the source and the drain coupled to the power supply line. The second transistor has a gate coupled to one of the source and the drain of the first transistor, one of a source and a drain coupled to the data line, and the other one of the source and the drain coupled to the control line.

Abstract translation: 一种半导体器件，包括：电阻性存储元件; 电耦合到所述电阻性存储元件的数据线; 控制线 电源线; 以及包括第一恒流元件，第一晶体管和第二晶体管的控制电路。 在控制电路中，第一晶体管具有耦合到数据线的栅极，耦合到第一恒流元件的源极和漏极之一，以及耦合到电源线的源极和漏极中的另一个。 第二晶体管具有耦合到第一晶体管的源极和漏极之一的栅极，耦合到数据线的源极和漏极中的一个，以及耦合到控制线的源极和漏极中的另一个。

公开(公告)号：US09236123B2

公开(公告)日：2016-01-12

申请号：US14495775

申请日：2014-09-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akiko Maeda ,  Shuichi Tsukada ,  Yusuke Jono

IPC: G11C11/00 ,  G11C13/00 ,  G11C7/04 ,  G11C16/20 ,  G11C29/00

CPC classification number: G11C13/0069 ,  G11C7/04 ,  G11C11/005 ,  G11C13/0002 ,  G11C13/004 ,  G11C16/20 ,  G11C29/70 ,  G11C2013/0054 ,  G11C2013/0083 ,  G11C2013/009

Abstract: A semiconductor device includes a memory cell array including a plurality of first and second memory cells each comprising a variable resistance element that establishes an electrical resistance that changes in response to an application of a write voltage after a forming voltage has been applied, the first memory cell to which the forming voltage is applied, and the second memory cell to which the forming voltage is not applied, and the second memory cell being configured to store one of first and second logic values constituting first information, the first and second logic values being different from each other.

Abstract translation: 半导体器件包括存储单元阵列，其包括多个第一和第二存储器单元，每个存储器单元包括可变电阻元件，该可变电阻元件建立响应于在施加形成电压之后施加写入电压而改变的电阻，第一存储器 施加成形电压的单元和不施加形成电压的第二存储单元，并且第二存储单元被配置为存储构成第一信息的第一和第二逻辑值之一，第一和第二逻辑值为 彼此不同。

公开(公告)号：US12237001B2

公开(公告)日：2025-02-25

申请号：US17700289

申请日：2022-03-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tetsuya Arai ,  Shuichi Tsukada ,  Shun Nishimura ,  Yoshinori Matsui

IPC: G11C11/4096 ,  G11C11/4093 ,  H03K19/003

Abstract: Apparatuses including output drivers and methods for providing output data signals are described. An example apparatus includes a high logic level driver, a low logic level driver, and an intermediate logic level driver. The high logic level driver is provided a first voltage and provides a high logic level voltage to a data terminal when activated. The low logic level driver is provided a second voltage and provides a low logic level voltage to the data terminal when activated. The intermediate logic level driver is provided a third voltage having a magnitude that is between the first and second voltages, and provides an intermediate logic level voltage to the data terminal when activated. Each of the high, low, and intermediate logic level drivers are configured to be respectively activated based on one or more of a plurality of control signals.

公开(公告)号：US11709523B2

公开(公告)日：2023-07-25

申请号：US17486429

申请日：2021-09-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenji Asaki ,  Shuichi Tsukada

IPC: G06F1/08 ,  H03B5/12 ,  G06F1/28 ,  G06F1/06 ,  G06F13/16 ,  G06F13/00 ,  G06F1/04 ,  G06F1/10

CPC classification number: G06F1/08 ,  G06F1/28 ,  H03B5/1209 ,  G06F1/04 ,  G06F1/06 ,  G06F1/10 ,  G06F13/00 ,  G06F13/1689

Abstract: In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.

公开(公告)号：US11057038B2

公开(公告)日：2021-07-06

申请号：US16656415

申请日：2019-10-17

Applicant: Micron Technology, Inc.

Inventor： Tetsuya Arai ,  Shuichi Tsukada ,  Junki Taniguchi

IPC: H03K19/00 ,  G11C5/14 ,  G11C7/10 ,  G11C29/02 ,  G11C29/50

Abstract: A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.

公开(公告)号：US20210201967A1

公开(公告)日：2021-07-01

申请号：US17133480

申请日：2020-12-23

Applicant: Micron Technology, Inc.

Inventor： Hiroyuki Matsuno ,  Shuichi Tsukada

IPC: G11C7/10 ,  G11C11/4091 ,  G11C8/18 ,  G11C11/4074 ,  G11C7/22 ,  G11C7/06 ,  G11C11/4072

Abstract: Apparatuses including input buffers and methods for operating input buffers are described. An example input buffer includes a plurality of input buffer circuits, each receiving input data and activated by a respective clock signal. An input buffer circuit includes a decision feedback equalizer (DFB) having adjustable capacitances and reference capacitances to set a reference level of the input buffer circuit. The capacitance of the adjustable capacitances may be set by a code. The DFB provides a capacitance of the adjustable capacitances to a first sense node and further provides a capacitance of the reference capacitances to a second sense node to set the reference level of the input buffer circuit. The input buffer circuit provides output data based on the input data and the reference level set by the DFE.