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公开(公告)号：US09734912B2
公开(公告)日：2017-08-15
申请号：US15208175
申请日：2016-07-12
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yung-Chun Li , Yu-Ming Chang , Ping-Hsien Lin , Hsiang-Pang Li
CPC classification number: G11C16/10 , G11C7/14 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0466 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/3445 , G11C16/3459 , G11C16/349 , G11C16/3495 , G11C2211/5634 , G11C2211/5641
Abstract: A method to operate a single bit per cell memory comprises erasing a group of memory cells establishing a first logical value by setting threshold voltages in a first range of threshold voltages. First writing, after said erasing, includes programming first selected memory cells to establish a second logical value by setting threshold voltages in a second range of threshold voltages, and saving a sensing state parameter to indicate a first read voltage. Second writing, after said first writing, includes programming second selected memory cells to establish the second logical value by setting threshold voltages in a third range of threshold voltages, and saving the sensing state parameter to indicate a second read voltage. After a number of writings including said first writing and said second writing reaches a threshold number for writing the group of memory cells, the group of memory cells can be erased.
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公开(公告)号：US12260130B2
公开(公告)日：2025-03-25
申请号：US18161900
申请日：2023-01-31
Applicant: MACRONIX International Co., Ltd.
Inventor： Hang-Ting Lue , Tzu-Hsuan Hsu , Teng-Hao Yeh , Chih-Chang Hsieh , Chun-Hsiung Hung , Yung-Chun Li
IPC: G06F17/16 , G06F3/06 , G06F7/49 , G06N3/00 , G11C7/06 , G11C7/10 , G11C7/18 , G11C8/14 , G11C16/04 , G11C16/24 , G11C16/28 , G11C27/00
Abstract: A memory device for CIM, applicable to a 3D AND-type flash memory, includes a memory array, input word line pairs, and a signal processing circuit. The memory array includes first and second pairs of memory cells. Each first pair of memory cells includes a first memory cell set coupled to a first GBL and a second memory cell set coupled to a second GBL. Each second pair of memory cells includes a third memory cell set coupled to the first GBL and a fourth memory cell set coupled to the second GBL. Each input word line pair includes a first input word line coupled to the first and the second memory cell sets, and a second input word line coupled to the third and the fourth memory cell sets s. The signal processing circuit is coupled to the first and second global bit lines.
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公开(公告)号：US12169702B2
公开(公告)日：2024-12-17
申请号：US17411938
申请日：2021-08-25
Applicant: MACRONIX International Co., Ltd.
Inventor： Bo-Rong Lin , Yung-Chun Li , Han-Wen Hu , Huai-Mu Wang
Abstract: An in-memory computing method and an in-memory computing apparatus are adapted to perform multiply-accumulate (MAC) operations on a memory by a processor. In the method, a pre-processing operation is respectively performed on input data and weight data to be written into input lines and memory cells of the memory to divide the input data and weight data into a primary portion and a secondary portion. The input data and the weight data divided into the primary portion and the secondary portion are written into the input lines and the memory cells in batches to perform the MAC operations and obtain a plurality of computation results. According to a numeric value of each of the computation results, the computation results are filtered. According to the portions to which the computation results correspond, a post-processing operation is performed on the filtered computation results to obtain output data.
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Patent Agency Ranking
公开(公告)号：US11663074B1
公开(公告)日：2023-05-30
申请号：US17528346
申请日：2021-11-17
Applicant: Macronix International Co., Ltd.
Inventor： Yu-Ming Huang , Yung-Chun Li
CPC classification number: G06F11/1016 , G06F3/0625 , G06F3/0655 , G06F3/0679 , G06F2201/805
Abstract: Systems, methods, and apparatus including computer-readable mediums for determining read voltages for memory systems are provided. In one aspect, a memory system includes a memory storing data and a memory controller coupled to the memory. The memory controller is configured to: obtain a first reading output of target memory data in the memory using a first read voltage, and in response to determining that the first reading output fails to pass an Error-Correcting Code (ECC) test, provide the first read voltage to the memory. The memory is configured to: determine a second read voltage based on the first read voltage and generate a second reading output of the target memory data using the second read voltage.
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公开(公告)号：US20230161556A1
公开(公告)日：2023-05-25
申请号：US17701725
申请日：2022-03-23
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Han-Wen Hu , Yung-Chun Li , Bo-Rong Lin , Huai-Mu Wang , Wei-Chen Wang
IPC: G06F7/544 , G06F7/527 , G06F7/72 , G06F12/0882 , G06F13/16
CPC classification number: G06F7/5443 , G06F7/5272 , G06F7/729 , G06F12/0882 , G06F13/1673
Abstract: A memory device and an operation method thereof are provided. The operation method includes: encoding an input data, sending an encoded input data to at least one page buffer, and reading out the encoded input data in parallel; encoding a first part and a second part of a weight data into an encoded first part and an encoded second part of the weight data, respectively, writing the encoded first part and the encoded second part of the weight data into a plurality of memory cells of the memory device, and reading out the encoded first part and the encoded second part of the weight data in parallel; multiplying the encoded input data with the encoded first part and the encoded second part of the weight data respectively to parallel generate a plurality of partial products; and accumulating the partial products to generate an operation result.
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公开(公告)号：US11386972B2
公开(公告)日：2022-07-12
申请号：US17073800
申请日：2020-10-19
Applicant: Macronix International Co., Ltd.
Inventor： Yung-Chun Li , Yu-Ming Huang , Chih-Huai Shih
Abstract: Systems, methods, and apparatus including computer-readable mediums for determining read voltages for memory systems with machine learning (ML) are provided. In one aspect, a memory system includes a memory and a memory controller configured to: obtain a first reading output of memory data using a first read voltage corresponding to a first set of parameters associated with the memory data; if the first reading output fails to pass an Error Correction Code (ECC) test, obtain a second reading output of the memory data using a second read voltage corresponding to a second set of parameters associated with the memory data and including the first set of parameters, the second read voltage being generated using at least one ML algorithm based on the second set of parameters; and if the second reading output passes the ECC test, output the second reading output as a target reading output of the memory data.
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公开(公告)号：US09627072B2
公开(公告)日：2017-04-18
申请号：US14857598
申请日：2015-09-17
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Yung-Chun Li , Hsiang-Pang Li , Yuan-Hao Chang , Tei-Wei Kuo
CPC classification number: G11C16/10 , G11C11/56 , G11C11/5628 , G11C11/5642 , G11C16/08 , G11C16/26 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5648
Abstract: A multiple-bit-per-cell, page mode memory comprises a plurality of physical pages, each physical page having N addressable pages p(n). Logic implements a plurality of selectable program operations to program an addressed page. Logic select one of the plurality of selectable program operations to program an addressed page in the particular physical page using a signal that indicates a logical status of another addressable page in the particular physical page. The logical status can indicate whether the other addressable page contains invalid data. The first program operation overwrites the other addressable page, and the second program operation preserves the other addressable page. The first program operation can execute more quickly than the second program operation. The logic can also be applied for programming multiple-bit-per-cell memory not configured in a page mode.
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公开(公告)号：US09025375B2
公开(公告)日：2015-05-05
申请号：US14060296
申请日：2013-10-22
Applicant: Macronix International Co., Ltd.
Inventor： Yu-Ming Chang , Yung-Chun Li , Hsing-Chen Lu , Hsiang-Pang Li , Cheng-Yuan Wang , Yuan-Hao Chang , Tei-Wei Kuo
CPC classification number: G06F12/0246 , G06F2212/7205 , G11C16/0483 , G11C16/16 , G11C16/3427
Abstract: Technology is described that supports reduced program disturb of nonvolatile memory. A three/two dimensional NAND array includes a plurality of pages, which are divided into a plurality of page groups. Access is allowed to memory cells within a first page group of a plurality of page groups in an erase block of the three dimensional NAND array, while access is minimized to memory cells within a second page group of the plurality of page groups in the erase block of the three/two dimensional NAND array. Pages in the same page group are physically nonadjacent with each other in the three/two dimensional NAND array.
Abstract translation: 描述了支持减少非易失性存储器的程序干扰的技术。 三/二维NAND阵列包括被分成多个页组的多页。 允许访问在三维NAND阵列的擦除块中的多个寻呼组的第一页组内的存储单元，同时访问最小化到擦除块中的多个页组的第二页组内的存储单元 的三/二维NAND阵列。 同一页组中的页面在三维/二维NAND阵列中彼此物理上不相邻。
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