公开(公告)号：US20090302398A1

公开(公告)日：2009-12-10

申请号：US12157556

申请日：2008-06-10

申请人： Bernhard Sell ,  Rishabh Mehandru

发明人： Bernhard Sell ,  Rishabh Mehandru

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/7834 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66621

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming a transistor comprising a metal gate disposed on a gate dielectric that is disposed on a substrate, and a source/drain region disposed adjacent a channel region of the transistor. The source/drain region comprises a source/drain extension comprising a vertex point, wherein a top surface of the channel region is substantially planar with the vertex point.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括形成包括设置在设置在衬底上的栅极电介质上的金属栅极的晶体管，以及邻近晶体管的沟道区域设置的源极/漏极区域。 源极/漏极区域包括源极/漏极延伸部分，其包括顶点，其中沟道区域的顶表面与顶点基本上是平面的。

公开(公告)号：US20080029834A1

公开(公告)日：2008-02-07

申请号：US11500628

申请日：2006-08-07

申请人： Bernhard Sell

发明人： Bernhard Sell

IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/00

CPC分类号： H01L29/4983 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  Y10S257/90

摘要： A multi-component low-k isolation spacer for a conductive region in a semiconductor structure is described. In one embodiment, a replacement isolation spacer process is utilized to enable the formation of a two-component low-k isolation spacer adjacent to a sidewall of a gate electrode in a MOS-FET device.

摘要翻译： 描述了用于半导体结构中的导电区域的多组分低k隔离间隔物。 在一个实施例中，替代隔离隔离器工艺被用于在MOS-FET器件中形成邻近栅电极的侧壁的双组分低k隔离隔离层。

公开(公告)号：US20060073659A1

公开(公告)日：2006-04-06

申请号：US11285639

申请日：2005-11-22

申请人： Bernhard Sell ,  Annette Sanger ,  Dirk Schumann

发明人： Bernhard Sell ,  Annette Sanger ,  Dirk Schumann

IPC分类号： H01L21/8242

CPC分类号： H01L27/10861 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/28518 ,  H01L21/31604 ,  H01L27/10814 ,  H01L28/60

摘要： The present invention relates to a novel method for fabricating a storage capacitor designed as a trench or a stacked capacitor and is used in particular in a DRAM memory cell. The method includes steps of forming a lower, metallic capacitor electrode, a storage dielectric and an upper capacitor electrode. The lower, metallic capacitor electrode is formed in a self-aligned manner on a silicon base material in such a way that uncovered silicon regions are first produced at locations at which the lower capacitor electrode will be formed, and then metal silicide is selectively formed on the uncovered silicon regions.

摘要翻译： 本发明涉及一种用于制造设计为沟槽或层叠电容器的存储电容器的新颖方法，特别用于DRAM存储单元。 该方法包括形成下部金属电容器电极，存储电介质和上部电容器电极的步骤。 下部金属电容器电极以自对准的方式形成在硅基材上，使得首先在将形成下电容器电极的位置处产生未覆盖的硅区域，然后选择性地形成金属硅化物 未覆盖的硅区域。

公开(公告)号：US06600680B2

公开(公告)日：2003-07-29

申请号：US10186599

申请日：2002-07-01

申请人： Bernhard Sell ,  Jürgen Lindolf ,  Martin Popp

发明人： Bernhard Sell ,  Jürgen Lindolf ,  Martin Popp

IPC分类号： G11C700

CPC分类号： G11C29/50012 ,  G01R27/2605 ,  G11C11/401 ,  G11C29/50

摘要： A ring oscillator has a multiplicity of inverters. An interconnect is connected between two of the inverters, and a storage capacitor to be measured, with its associated lead resistor, is coupled to the interconnect either via an interconnect or a transistor can selectively coupled and decouple the capacitor and the lead resistance. A measuring device is connected up to the ring oscillator and is used to determine a value for the oscillation frequency of the ring oscillator on the basis of which a value for the time constant of the storage capacitor can be determined.

公开(公告)号：US06548350B2

公开(公告)日：2003-04-15

申请号：US10093039

申请日：2002-03-07

申请人： Bernhard Sell ,  Dirk Schumann ,  Josef Willer

发明人： Bernhard Sell ,  Dirk Schumann ,  Josef Willer

IPC分类号： H01L218242

CPC分类号： H01L28/91 ,  H01L27/10852

摘要： The capacitor is arranged on the surface of a substrate. A first capacitor electrode has a middle part and a side part, which point vertically upwards, are arranged beside each other and are connected with each other via an upper part located above said middle part and said side part. The middle part is longer than the side part and is connected with other components of the circuit configuration located below said middle part and said side part. The first capacitor electrode is provided with a capacitor dielectric. A second capacitor electrode borders the capacitor dielectric.

公开(公告)号：US09711410B2

公开(公告)日：2017-07-18

申请号：US14569166

申请日：2014-12-12

申请人： Bernhard Sell

发明人： Bernhard Sell

IPC分类号： H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/16 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L21/823431 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/823412 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

摘要： Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

公开(公告)号：US09224602B2

公开(公告)日：2015-12-29

申请号：US13976088

申请日：2011-12-29

申请人： Aravind S. Killampalli ,  Charles H. Wallace ,  Bernhard Sell

发明人： Aravind S. Killampalli ,  Charles H. Wallace ,  Bernhard Sell

IPC分类号： G03F7/40 ,  H01L21/263 ,  H01L21/027 ,  H01L21/033

CPC分类号： H01L21/2636 ,  G03F7/40 ,  H01L21/0273 ,  H01L21/0337

摘要： Techniques are disclosed for sub-second annealing a lithographic feature to, for example, tailor or otherwise selectively alter its profile in one, two, or three dimensions. Alternatively, or in addition to, the techniques can be used, for example, to smooth or otherwise reduce photoresist line width/edge roughness and/or to reduce defect density. In some cases, the sub-second annealing process has a time-temperature profile that can effectively change the magnitude of resist shrinkage in one or more dimensions or otherwise modify the resist in a desired way (e.g., smooth the resist). The techniques may be implemented, for example, with any type of photoresist (e.g., organic, inorganic, hybrid, molecular photoresist materials) and can be used in forming, for instance, processor microarchitectures, memory circuitry, logic arrays, and numerous other digital/analog/hybrid integrated semiconductor devices.

摘要翻译： 公开了用于将光刻特征的亚秒级退火的技术，例如，以一维，二维或三维的方式选择性地改变其轮廓。 或者，或者除了这些技术之外，可以使用技术来平滑或以其它方式减少光致抗蚀剂线宽/边缘粗糙度和/或降低缺陷密度。 在一些情况下，亚秒级退火工艺具有时间 - 温度分布，其可以有效地改变一个或多个维度中的抗蚀剂收缩的大小，或以所需的方式（例如使光刻胶光滑）修饰抗蚀剂。 这些技术可以例如使用任何类型的光致抗蚀剂（例如有机，无机，杂化，分子光刻胶材料）来实现，并且可以用于形成例如处理器微架构，存储器电路，逻辑阵列和许多其它数字 /模拟/混合集成半导体器件。

公开(公告)号：US20140117489A1

公开(公告)日：2014-05-01

申请号：US13976088

申请日：2011-12-29

申请人： Aravind S. Killampalli ,  Charles H. Wallace ,  Bernhard Sell

发明人： Aravind S. Killampalli ,  Charles H. Wallace ,  Bernhard Sell

IPC分类号： H01L21/263

CPC分类号： H01L21/2636 ,  G03F7/40 ,  H01L21/0273 ,  H01L21/0337

摘要： Techniques are disclosed for sub-second annealing a lithographic feature to, for example, tailor or otherwise selectively alter its profile in one, two, or three dimensions. Alternatively, or in addition to, the techniques can be used, for example, to smooth or otherwise reduce photoresist line width/edge roughness and/or to reduce defect density. In some cases, the sub-second annealing process has a time-temperature profile that can effectively change the magnitude of resist shrinkage in one or more dimensions or otherwise modify the resist in a desired way (e.g., smooth the resist). The techniques may be implemented, for example, with any type of photoresist (e.g., organic, inorganic, hybrid, molecular photoresist materials) and can be used in forming, for instance, processor microarchitectures, memory circuitry, logic arrays, and numerous other digital/analog/hybrid integrated semiconductor devices.

摘要翻译： 公开了用于将光刻特征的亚秒级退火的技术，例如，在一个，两个或三个维度上定制或以其它方式选择性地改变其轮廓。 或者，或者除了这些技术之外，可以使用技术来平滑或以其它方式减少光致抗蚀剂线宽/边缘粗糙度和/或降低缺陷密度。 在一些情况下，亚秒级退火工艺具有时间 - 温度分布，其可以有效地改变一个或多个维度中的抗蚀剂收缩的大小，或以所需的方式（例如使光刻胶光滑）改性抗蚀剂。 这些技术可以例如使用任何类型的光致抗蚀剂（例如有机，无机，杂化，分子光刻胶材料）来实现，并且可以用于形成例如处理器微架构，存储器电路，逻辑阵列和许多其它数字 /模拟/混合集成半导体器件。

公开(公告)号：US08154087B2

公开(公告)日：2012-04-10

申请号：US13107739

申请日：2011-05-13

申请人： Ted E. Cook, Jr. ,  Bernhard Sell ,  Anand Murthy

发明人： Ted E. Cook, Jr. ,  Bernhard Sell ,  Anand Murthy

IPC分类号： H01L27/088

CPC分类号： H01L29/7848 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/7834

摘要： A multi-component strain-inducing semiconductor region is described. In an embodiment, formation of such a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In one embodiment, the multi-component strain-inducing material region comprises a first portion and a second portion which are separated by an interface. In a specific embodiment, the concentration of charge-carrier dopant impurity atoms of the two portions are different from one another at the interface.

摘要翻译： 描述了多组分应变诱导半导体区域。 在一个实施方案中，在与晶体衬底横向相邻的这种应变诱导半导体区域的形成导致赋予晶体衬底的单轴应变，从而提供应变晶体衬底。 在一个实施例中，多组分应变诱导材料区域包括由界面分离的第一部分和第二部分。 在具体实施方案中，两部分的电荷 - 载流子掺杂剂杂质原子的浓度在界面处彼此不同。

公开(公告)号：US20100109046A1

公开(公告)日：2010-05-06

申请号：US12290809

申请日：2008-11-03

申请人： Rishabh Mehandru ,  Bernhard Sell ,  Anand Murthy ,  Lucian Shifren

发明人： Rishabh Mehandru ,  Bernhard Sell ,  Anand Murthy ,  Lucian Shifren

IPC分类号： H01L29/778 ,  H01L21/336

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/76804 ,  H01L21/76814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7834

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a tapered contact opening in an ILD disposed on a substrate, wherein a source/drain contact area is exposed, preamorphizing a portion of a source drain region of the substrate, implanting boron into the source/drain region through the tapered contact opening, forming a metal layer on the source/drain contact area, and then annealing the metal layer to form a metal silicide.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括在设置在衬底上的ILD中形成锥形接触开口，其中暴露源极/漏极接触区域，对基底的源极漏极区域的一部分进行预变质，通过锥形 接触开口，在源极/漏极接触区域上形成金属层，然后退火金属层以形成金属硅化物。