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    MEMORY ARRAYS AND METHODS USED IN FORMING A MEMORY ARRAY
    22.
    发明申请
    MEMORY ARRAYS AND METHODS USED IN FORMING A MEMORY ARRAY 有权

    公开(公告)号：US20210202515A1

    公开(公告)日：2021-07-01

    申请号：US16728723

    申请日：2019-12-27

    Applicant: Micron Technology, Inc.

    Inventor： Anilkumar Chandolu ,  S.M. Istiaque Hossain ,  Darwin A. Clampitt ,  Arun Kumar Dhayalan ,  Kevin R. Gast ,  Christopher Larsen ,  Prakash Rau Mokhna Rau ,  Shashank Saraf

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising memory-block regions having channel-material strings therein. Conductor-material contacts are directly against the channel material of individual of the channel-material strings. First insulator material is formed directly above the conductor-material contacts. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is formed directly above the first insulator material and the conductor-material contacts. The second insulator material is devoid of each of the (a) and (b). Third insulator material is formed directly above the second insulator material, the first insulator material, and the conductor-material contacts. The third insulator material comprises at least one of the (a) and (b). At least one horizontally-elongated isolation structure is formed in the first and second insulator materials and in a top part of the stack in individual of the memory-block regions. Additional methods, including structure independent of method, are disclosed.

    ELECTRONIC DEVICES COMPRISING A SOURCE BELOW MEMORY CELLS AND RELATED SYSTEMS
    23.
    发明申请
    ELECTRONIC DEVICES COMPRISING A SOURCE BELOW MEMORY CELLS AND RELATED SYSTEMS 有权

    公开(公告)号：US20210167087A1

    公开(公告)日：2021-06-03

    申请号：US17172956

    申请日：2021-02-10

    Applicant: Micron Technology, Inc.

    Inventor： Darwin A. Clampitt ,  David H. Wells ,  John D. Hopkins ,  Kevin Y. Titus

    IPC: H01L27/11582 ,  H01L21/02 ,  H01L27/11521 ,  H01L29/08 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11556 ,  H01L29/10 ,  H01L29/66 ,  H01L21/28

    Abstract: A method of forming a semiconductor device comprises forming sacrificial structures and support pillars on a material. Tiers are formed over the sacrificial structures and support pillars and tier pillars and tier openings are formed to expose the sacrificial structures. One or more of the tier openings comprises a greater critical dimension than the other tier openings. The sacrificial structures are removed to form a cavity. A cell film is formed over sidewalls of the tier pillars, the cavity, and the one or more tier openings. A fill material is formed in the tier openings and adjacent to the cell film and a portion removed from the other tier openings to form recesses adjacent to an uppermost tier. Substantially all of the fill material is removed from the one or more tier openings. A doped polysilicon material is formed in the recesses and the one or more tier openings. A conductive material is formed in the recesses and in the one or more tier openings. An opening is formed in a slit region and a dielectric material is formed in the opening. Additional methods, semiconductor devices, and systems are disclosed.

    CONTACT FORMATION FOR A MEMORY DEVICE
    24.
    发明公开
    CONTACT FORMATION FOR A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240357837A1

    公开(公告)日：2024-10-24

    申请号：US18642555

    申请日：2024-04-22

    Applicant: Micron Technology, Inc.

    Inventor： Darwin A. Clampitt ,  Stephen W. Russell ,  Steven P. Turini ,  Farrell M. Good ,  Kolya Yastrebenetsky ,  Nirav Vora ,  Zhao Zhao

    IPC: H10B63/00 ,  H10B63/10

    CPC classification number: H10B63/845 ,  H10B63/10

    Abstract: Methods, systems, and devices for contact formation for a memory device are described. A memory device manufacturing operation may include forming bit lines and word lines in a same step. In some cases, the memory device may include word line contact portions that couple respective word lines with respective word line contacts located below the word lines. For example, the word line contact portions may be located between word lines and a substrate of the memory array. In such cases, the processing step may be used for formation of word lines, bit lines, and word line contact portions. Additionally, or alternatively, the memory device manufacturing operation may include forming a sacrificial ring around bit line contacts, which may isolate bit line contacts from a nitride layer.

    Memory Circuitry And Methods Used In Forming Memory Circuitry
    26.
    发明公开
    Memory Circuitry And Methods Used In Forming Memory Circuitry 审中-公开

    公开(公告)号：US20240315027A1

    公开(公告)日：2024-09-19

    申请号：US18602313

    申请日：2024-03-12

    Applicant: Micron Technology, Inc.

    Inventor： Darwin A. Clampitt ,  Collin Howder ,  Matthew J. King

    IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

    CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

    Abstract: Memory circuitry comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises laterally-spaced memory blocks. The memory blocks individually comprise sub-blocks in an upper portion thereof. Strings of memory cells are included and that comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. A conductive-material tier is included and that comprises conductive material in the upper portions. The conductive material extends downwardly from the conductive-material tier to below the conductive-material tier. Sub-block trenches in the upper portions are individually between immediately-laterally-adjacent of the sub-blocks and extend through the conductive-material tier. Select gates of select-gate transistors are in individual of the sub-blocks operatively alongside channel material of the select-gate transistors. The select gates comprise the conductive material of the conductive-material tier and the conductive material extending downwardly from the conductive-material tier to below the conductive-material tier alongside the channel material of the select-gate transistors. Methods are also disclosed.

    ENGINEERED SEMICONDUCTOR SUBSTRATE
    28.
    发明公开
    ENGINEERED SEMICONDUCTOR SUBSTRATE 审中-公开

    公开(公告)号：US20240203804A1

    公开(公告)日：2024-06-20

    申请号：US18514563

    申请日：2023-11-20

    Applicant: Micron Technology, Inc.

    Inventor： Darwin A. Clampitt ,  Roger W. Lindsay ,  Lisa M. Clampitt

    IPC: H01L23/13 ,  B28D5/00 ,  H01L21/18 ,  H01L21/304 ,  H01L23/14

    CPC classification number: H01L23/13 ,  B28D5/0005 ,  H01L21/187 ,  H01L21/304 ,  H01L23/147 ,  H01L25/0657

    Abstract: A semiconductor device assembly is provided. The semiconductive device assembly includes a semiconductor die with a substrate having an engineered portion and a semiconductive portion. The engineered portion includes one or more of: a sintered material, a corrugated material, oriented strands of material compressed to form a solid structure, layers of material compressed to form a solid structure, or a material arranged to form one or more planar trusses. The semiconductive portion is adhered directly to the engineered portion. A layer of dielectric material is disposed at the semiconductive portion, and circuitry is disposed at the layer of dielectric material. In doing so, a cost-efficient and mechanically robust semiconductor device may be assembled.

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