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    Apparatuses having a vertical memory cell
    21.
    发明授权
    Apparatuses having a vertical memory cell 有权
    具有垂直存储单元的装置

    公开(公告)号：US09577092B2

    公开(公告)日：2017-02-21

    申请号：US14517261

    申请日：2014-10-17

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Rajesh N. Gupta ,  Srinivas Pulugurtha ,  Chandra V. Mouli ,  Wolfgang Mueller

    IPC: H01L29/78 ,  G11C11/40 ,  H01L27/02 ,  H01L27/105 ,  H01L29/66 ,  H01L27/108

    CPC classification number: H01L29/7827 ,  G11C11/40 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666

    Abstract: Methods, apparatuses, and systems for providing a body connection to a vertical access device. The vertical access device may include a digit line extending along a substrate to a digit line contact pillar, a body connection line extending along the substrate to a body connection line contact pillar, a body region disposed on the body connection line, an electrode disposed on the body region, and a word line extending to form a gate to the body region. A method for operation includes applying a first voltage to the body connection line, and applying a second voltage to the word line to cause a conductive channel to form through the body region. A memory cell array may include a plurality of vertical access devices.

    Abstract translation: 用于向垂直存取装置提供身体连接的方法，装置和系统。 垂直进入装置可以包括沿着基板延伸到数字线接触柱的数字线，沿着基板延伸到主体连接线接触柱的主体连接线，设置在主体连接线上的主体区域，设置在主体连接线上的电极 身体区域和延伸以形成到身体区域的门的字线。 一种操作方法包括：将第一电压施加到身体连接线，以及向该字线施加第二电压，以使导电通道通过身体区域形成。 存储单元阵列可以包括多个垂直存取装置。

    Resistance variable element methods and apparatuses
    23.
    发明授权
    Resistance variable element methods and apparatuses 有权
    电阻可变元件的方法和装置

    公开(公告)号：US09373399B2

    公开(公告)日：2016-06-21

    申请号：US13947807

    申请日：2013-07-22

    Applicant: Micron Technology, Inc.

    Inventor： Seshadri K. Kolluri ,  Rajesh N. Gupta

    IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

    CPC classification number: G11C13/0097 ,  G11C11/56 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0092 ,  G11C2213/79

    Abstract: Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a first data line voltage and a first control gate voltage, and then performs a second operation on a second resistance variable element using the common source voltage, a second data line voltage and a second control gate voltage. Additional apparatus and methods are described.

    Abstract translation: 公开了一种装置和方法，包括使用公共源电压，第一数据线电压和第一控制栅极电压对第一电阻可变元件执行第一操作的方法，然后对第二电阻可变元件执行第二操作 使用公共源电压，第二数据线电压和第二控制栅极电压。 描述附加的装置和方法。

    Gated Bipolar Junction Transistors, Memory Arrays, and Methods of Forming Gated Bipolar Junction Transistors
    24.
    发明申请
    Gated Bipolar Junction Transistors, Memory Arrays, and Methods of Forming Gated Bipolar Junction Transistors 审中-公开
    门极双极结晶体管，存储器阵列和形成门极双极结晶体管的方法

    公开(公告)号：US20150155283A1

    公开(公告)日：2015-06-04

    申请号：US14613876

    申请日：2015-02-04

    Applicant: Micron Technology, Inc.

    Inventor： Rajesh N. Gupta ,  Farid Nemati ,  Scott T. Robins

    IPC: H01L27/102 ,  H01L21/8229 ,  H01L21/02 ,  H01L29/732 ,  H01L29/739 ,  H01L29/16

    CPC classification number: H01L27/1026 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/8229 ,  H01L27/1023 ,  H01L27/1024 ,  H01L27/10802 ,  H01L29/1608 ,  H01L29/73 ,  H01L29/732 ,  H01L29/735 ,  H01L29/7391 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.

    Abstract translation: 一些实施例包括门极双极结型晶体管。 晶体管可以包括在集电极区域和发射极区域之间的基极区域; 其中B-C结位于基极区和集电极区的界面处，并且B-E结位于基极区和发射极区的界面处。 晶体管可以包括在一个或多个基极，发射极和集电极区内具有至少1.2eV的带隙的材料。 栅极晶体管可以包括沿着基极区域的栅极并且通过电介质材料与基极区域间隔开，栅极不与B-C结或B-E结重叠。 一些实施例包括包含门极双极结型晶体管的存储器阵列。 一些实施例包括形成门控双极结型晶体管的方法。

    Thyristors
    25.
    发明申请
    Thyristors 有权
    晶闸管

    公开(公告)号：US20130314986A1

    公开(公告)日：2013-11-28

    申请号：US13957304

    申请日：2013-08-01

    Applicant: Micron Technology, Inc.

    Inventor： Farid Nemati ,  Scott T. Robins ,  Rajesh N. Gupta

    IPC: G11C11/39 ,  H01L21/28

    CPC classification number: G11C11/39 ,  H01L21/28008 ,  H01L21/30604 ,  H01L21/76224 ,  H01L27/0817 ,  H01L27/1027 ,  H01L29/7455 ,  H01L29/749

    Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.

    Abstract translation: 一些实施例包括具有第一和第二电极区域，第一和第二基极区域以及在至少一个区域中具有至少1.2eV的带隙的材料的晶闸管。 第一基极区域在第一电极区域和第二基极区域之间，第二基极区域在第二电极区域和第一基极区域之间。 第一基区在第一结处与第一电极区相接，并且在第二结处与第二基区交界。 第二基极区域在第三结区与第二电极区域相接合。 栅极沿着第一基极区域，并且在一些实施例中不与第一和第二结点重叠。 一些实施例包括编程晶闸管的方法，一些实施例包括形成晶闸管的方法。

    Systems and methods for generating logical-to-physical tables for wear-leveling
    26.
    发明授权
    Systems and methods for generating logical-to-physical tables for wear-leveling 有权

    公开(公告)号：US12260092B2

    公开(公告)日：2025-03-25

    申请号：US17903772

    申请日：2022-09-06

    Applicant: Micron Technology, Inc.

    Inventor： Rajesh N. Gupta

    IPC: G06F3/06 ,  G06F12/1009

    Abstract: As described herein, an apparatus may include a memory that includes a first portion, a second portion, and a third portion. The apparatus may also include a memory controller that includes a first logical-to-physical table stored in a buffer memory. The memory controller may determine that the first portion is accessed sequential to the second portion and may adjust the first logical-to-physical table to cause a memory transaction performed by the memory controller to access the third portion as opposed to the first portion.

    Thyristor memory and methods of operation
    30.
    发明授权
    Thyristor memory and methods of operation 有权
    晶闸管记忆和操作方法

    公开(公告)号：US09384814B2

    公开(公告)日：2016-07-05

    申请号：US14451097

    申请日：2014-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Rajesh N. Gupta

    IPC: G11C11/34 ,  G11C11/39 ,  B82Y10/00 ,  G11C7/00

    CPC classification number: G11C11/39 ,  B82Y10/00 ,  G11C7/00

    Abstract: Apparatuses and methods can include write schemes for a thyristor memory cell in which an access pulse applied to the gate of the thyristor memory cell is adjusted relative to the data pulse to write data into the thyristor memory cell. Some of the write schemes may substantially reduce or eliminate an unselected data line disturb. In various embodiments, the thyristor memory cell can be structured with two control nodes and its cathode or anode coupled to a reference voltage node common to all thyristor memory cells in a memory array. Additional apparatuses and methods are disclosed.

    Abstract translation: 装置和方法可以包括用于晶闸管存储单元的写入方案，其中施加到晶闸管存储单元的栅极的访问脉冲相对于数据脉冲被调整以将数据写入晶闸管存储单元。 一些写入方案可以显着地减少或消除未选择的数据线干扰。 在各种实施例中，晶闸管存储单元可以由两个控制节点构成，其阴极或阳极耦合到存储器阵列中所有可控硅存储器单元公共的参考电压节点。 公开了附加的装置和方法。

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