公开(公告)号：US08709866B2

公开(公告)日：2014-04-29

申请号：US13963866

申请日：2013-08-09

Applicant: Micron Technology, Inc.

Inventor： Setho Sing Fee ,  Lim Thiam Chye ,  Tongbi Jiang

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L21/20 ,  H01L21/311

CPC classification number: H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages.

Abstract translation: 一些实施例包括组装集成电路封装的方法，其中在半导体管芯的接合焊盘区域上形成至少两个不同的导电层，并且其中与插入件相关联的导电突起通过金球结合到 至少两个导电层。 导电层可以包括银，金，铜，铬，镍，钯，铂，钽，钛，钒和钨中的一种或多种。 在一些实施例中，接合焊盘区域可以包括铝，导电层的内部可以包括镍，导电层的外部可以包括金，与中介层相关联的导电突起可以包括金; 并且热超声键合可以包括插入物突起与金球的金 - 金结合，以及外导体层与金球的金 - 金结合。 一些实施例包括集成电路封装。

公开(公告)号：US11869809B2

公开(公告)日：2024-01-09

申请号：US17015003

申请日：2020-09-08

Applicant: Micron Technology, Inc.

Inventor： Jin Li ,  Tongbi Jiang

IPC: H01L21/768 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683

CPC classification number: H01L21/76898 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L21/6836 ,  H01L24/16 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05025 ,  H01L2224/0557 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/27416 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00014 ,  H01L2924/0103 ,  H01L2924/014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/0002 ,  H01L2224/05552 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05611 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05664 ,  H01L2924/00014 ,  H01L2224/05111 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05139 ,  H01L2924/00014 ,  H01L2224/05144 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014 ,  H01L2224/05155 ,  H01L2924/00014 ,  H01L2224/05164 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/05169 ,  H01L2924/00014 ,  H01L2224/05171 ,  H01L2924/00014 ,  H01L2224/05181 ,  H01L2924/00014 ,  H01L2224/05184 ,  H01L2924/00014

Abstract: A semiconductor component includes a semiconductor substrate, conductive vias in the substrate having terminal portions, a polymer layer on the substrate and back side conductors formed by the terminal portions of the conductive vias embedded in the polymer layer. A stacked semiconductor component includes a plurality of components having aligned conductive vias in electrical communication with one another.

公开(公告)号：US20230197690A1

公开(公告)日：2023-06-22

申请号：US18175284

申请日：2023-02-27

Applicant: Micron Technology, Inc.

Inventor： Tongbi Jiang ,  Yong Poo Chia

IPC: H01L25/07 ,  H01L25/00 ,  H01L23/31 ,  H01L23/48 ,  H01L21/768 ,  H01L21/82 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L25/071 ,  H01L21/82 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L25/105 ,  H01L2221/68359 ,  H01L2224/20 ,  H01L2224/838 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/83193 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/06548 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043

Abstract: A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material.

公开(公告)号：US08729590B2

公开(公告)日：2014-05-20

申请号：US13870740

申请日：2013-04-25

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Tongbi Jiang

IPC: H01L33/00

CPC classification number: H01L33/10 ,  H01L33/0079 ,  H01L33/0095 ,  H01L33/46

Abstract: Solid state lighting devices having side reflectivity and associated methods of manufacturing are disclosed herein. In one embodiment, a method of forming a solid state lighting device includes attaching a solid state emitter to a support substrate, mounting the solid state emitter and support substrate to a temporary carrier, and cutting kerfs through the solid state emitter and the substrate to separate individual dies. The solid state emitter can have a first semiconductor material, a second semiconductor material, and an active region between the first and second semiconductor materials. The individual dies can have sidewalls that expose the first semiconductor material, active region and second semiconductor material. The method can further include applying a reflective material into the kerfs and along the sidewalls of the individual dies.

Abstract translation: 本文公开了具有侧反射率和相关制造方法的固态照明装置。 在一个实施例中，形成固态照明装置的方法包括将固态发射器附接到支撑衬底，将固态发射器和支撑衬底安装到临时载体上，以及通过固态发射器和衬底切割缝隙以分离 个人死亡 固态发射器可以具有第一半导体材料，第二半导体材料和第一和第二半导体材料之间的有源区。 各个管芯可以具有露出第一半导体材料，有源区和第二半导体材料的侧壁。 该方法还可以包括将反射材料施加到切口中并且沿着各个模具的侧壁。

公开(公告)号：US20130330882A1

公开(公告)日：2013-12-12

申请号：US13963866

申请日：2013-08-09

Applicant: Micron Technology, Inc.

Inventor： Setho Sing Fee ,  Lim Thiam Chye ,  Tongbi Jiang

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages.

Abstract translation: 一些实施例包括组装集成电路封装的方法，其中在半导体管芯的接合焊盘区域上形成至少两个不同的导电层，并且其中与插入件相关联的导电突起通过金球结合到 至少两个导电层。 导电层可以包括银，金，铜，铬，镍，钯，铂，钽，钛，钒和钨中的一种或多种。 在一些实施例中，接合焊盘区域可以包括铝，导电层的内部可以包括镍，导电层的外部可以包括金，与中介层相关联的导电突起可以包括金; 并且热超声键合可以包括插入物突起与金球的金 - 金结合，以及外导体层与金球的金 - 金结合。 一些实施例包括集成电路封装。