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    Pillar-last methods for forming semiconductor devices
    23.
    发明授权
    Pillar-last methods for forming semiconductor devices 有权

    公开(公告)号：US11631630B2

    公开(公告)日：2023-04-18

    申请号：US17175006

    申请日：2021-02-12

    Applicant: Micron Technology, Inc.

    Inventor： Anilkumar Chandolu ,  Wayne H. Huang ,  Sameer S. Vadhavkar

    IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L21/683 ,  H01L23/31

    Abstract: Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.

    Package cooling by coil cavity
    24.
    发明授权
    Package cooling by coil cavity 有权

    公开(公告)号：US11239129B2

    公开(公告)日：2022-02-01

    申请号：US17006740

    申请日：2020-08-28

    Applicant: Micron Technology, Inc.

    Inventor： Andrew M. Bayless ,  Wayne H. Huang ,  Owen R. Fay

    IPC: H01L23/31 ,  H01L23/473 ,  H01L21/56 ,  H01L23/36 ,  H01L23/467

    Abstract: A semiconductor device assembly can include a first die package comprising a bottom side; a top side; and lateral sides extending between the top and bottom sides. The assembly can include an encapsulant material encapsulating the first die package. In some embodiments, the assembly includes a cooling cavity in the encapsulant material. The cooling cavity can have a first opening; a second opening; and an elongate channel extending from the first opening to the second opening. In some embodiments, the elongate channel surrounds at least two of the lateral sides of the first die package. In some embodiments, the elongate channel is configured to accommodate a cooling fluid.

    UNIFORM BACK SIDE EXPOSURE OF THROUGH-SILICON VIAS
    26.
    发明申请
    UNIFORM BACK SIDE EXPOSURE OF THROUGH-SILICON VIAS 审中-公开

    公开(公告)号：US20180033641A1

    公开(公告)日：2018-02-01

    申请号：US15729391

    申请日：2017-10-10

    Applicant: Micron Technology, Inc.

    Inventor： Jaspreet S. Gandhi ,  Wayne H. Huang

    IPC: H01L21/321 ,  H01L21/768

    CPC classification number: H01L21/3212 ,  H01L21/7684 ,  H01L21/76898

    Abstract: Systems and methods for uniform back side exposure of through-silicon vias (TSVs) are disclosed. In one embodiment, a semiconductor device comprises a substrate having a front side with circuit elements formed thereon, and a back side opposite the front side. A TSV extends between the front side and the back side of the substrate, and a dummy feature is disposed over the back side of the substrate, the dummy feature laterally spaced apart from the TSV and substantially coplanar with the TSV. In another embodiment, a semiconductor device comprises a substrate having a TSV formed therethrough, with a control material disposed over the back side of the substrate, the TSV substantially coplanar with the control material.

    DEVICES, SYSTEMS, AND METHODS RELATED TO PLANARIZING SEMICONDUCTOR DEVICES AFTER FORMING OPENINGS
    28.
    发明申请
    DEVICES, SYSTEMS, AND METHODS RELATED TO PLANARIZING SEMICONDUCTOR DEVICES AFTER FORMING OPENINGS 审中-公开
    在形成开口之后平面化半导体器件的器件，系统和方法

    公开(公告)号：US20150206801A1

    公开(公告)日：2015-07-23

    申请号：US14607647

    申请日：2015-01-28

    Applicant: Micron Technology, Inc.

    Inventor： Wayne H. Huang ,  Anurag Jindal

    IPC: H01L21/768 ,  H01L21/02 ,  H01L21/304 ,  H01L21/321

    CPC classification number: H01L21/76898 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/304 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/743 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76883

    Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stop layer and a dielectric liner including dielectric material along sidewalls of openings, e.g., through-substrate openings, of the semiconductor device and excess dielectric material outside the openings. The method further includes forming a metal layer including metal plugs within the openings and excess metal. The excess metal and the excess dielectric material are simultaneously chemically-mechanically removed using a slurry including ceria and ammonium persulfate. The slurry is selected to cause selectivity for removing the excess dielectric material relative to the stop layer greater than about 5:1 as well as selectivity for removing the excess dielectric material relative to the excess metal from about 0.5:1 to about 1.5:1.

    Abstract translation: 本文公开了制造半导体器件的方法。 根据特定实施例配置的方法包括形成包含电介质材料的阻挡层和电介质衬垫，所述阻挡层和电介质衬垫沿着半导体器件的开口的侧壁（例如贯穿衬底开口）和开口外的多余电介质材料。 该方法还包括在开口内形成包括金属塞的金属层和多余的金属。 使用包括二氧化铈和过硫酸铵的浆料同时化学机械地除去多余的金属和过量的电介质材料。 选择浆料以引起相对于止挡层去除多余电介质材料的选择性大于约5:1，以及相对于多余金属从约0.5:1至约1.5:1去除多余电介质材料的选择性。

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