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公开(公告)号：US09361955B2
公开(公告)日：2016-06-07
申请号：US13387714
申请日：2011-01-27
申请人： Naveen Muralimanohar , Aniruddha Nagendran Udipi , Niladrish Chatterjee , Rajeev Balasubramonian , Alan Lynn Davis , Norman Paul Jouppi
发明人： Naveen Muralimanohar , Aniruddha Nagendran Udipi , Niladrish Chatterjee , Rajeev Balasubramonian , Alan Lynn Davis , Norman Paul Jouppi
CPC分类号： G06F3/0625 , G06F3/0634 , G06F3/0658 , G06F3/0673 , G06F11/1088 , G06F12/0802 , G06F12/0893 , G06F2212/1028 , G06F2212/3042 , G06F2212/305 , G11C5/04 , G11C7/10 , G11C8/12 , G11C11/4082 , Y02D10/13
摘要： An example apparatus includes a row address register to store a row address corresponding to a row in a memory array. The example apparatus also includes a row decoder coupled to the row address register to assert a signal on a wordline of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.
摘要翻译： 示例性装置包括用于存储对应于存储器阵列中的行的行地址的行地址寄存器。 示例性装置还包括耦合到行地址寄存器的行解码器，以在存储器接收到列地址之后对该行的字线进行断言。 此外，示例性装置包括列解码器，用于基于列地址和在字线上断言的信号选择性地激活行的一部分。
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公开(公告)号：US20150162078A1
公开(公告)日：2015-06-11
申请号：US14408512
申请日：2012-06-28
CPC分类号： G11C11/5678 , G11C7/1057 , G11C11/56 , G11C11/5628 , G11C11/5642 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C16/06 , G11C16/26 , G11C2211/5642
摘要： A multi-level cell memory includes a memory cell that stores two or more bits of information; a sensing circuit coupled to the memory cell; and a row buffer structure comprising a split page buffer having a first page buffer and a second page buffer. The sensing circuit operates to read from and write to the memory device, places a first bit in one of the first page buffer and the second page buffer, and places the second bit in one of the first page buffer and the second page buffer.
摘要翻译： 多级单元存储器包括存储两个或更多位信息的存储单元; 耦合到所述存储单元的感测电路; 以及包括具有第一页缓冲器和第二页缓冲器的分页页缓冲器的行缓冲器结构。 感测电路操作以读取和写入存储器件，将第一位置于第一页缓冲器和第二页缓冲器之一中，并将第二位置于第一页缓冲器和第二页缓冲器之一中。
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公开(公告)号：US20150082122A1
公开(公告)日：2015-03-19
申请号：US14396327
申请日：2012-05-31
申请人： Aniruddha Nagendran Udipi , Naveen Muralimanohar , Norman Paul Jouppi , Alan Lynn Davis , Rajeev Balasubramonian
发明人： Aniruddha Nagendran Udipi , Naveen Muralimanohar , Norman Paul Jouppi , Alan Lynn Davis , Rajeev Balasubramonian
IPC分类号： G06F11/10
CPC分类号： G06F11/1064 , G06F11/1012 , G06F11/1044 , G06F11/108 , G11C2029/0411
摘要： A system may use local error detection (LED) and global error correction (GEC) information to check data fidelity and correct an error. The LED may be calculated per cache line segment of data associated with a rank of a memory. Data fidelity may be checked in response to a memory read operation, based on the LED information, to identify a presence of an error and the location of the error among cache line segments of the rank. The cache line segment having the error may be corrected based on the GEC, in response to identifying the error.
摘要翻译： 系统可以使用本地错误检测（LED）和全局纠错（GEC）信息来检查数据保真度并纠正错误。 可以根据与存储器的等级相关联的数据的每个高速缓存行段来计算LED。 可以基于LED信息响应于存储器读取操作来检查数据保真度，以识别错误的存在以及该级别的高速缓存行段之间的错误位置。 响应于识别错误，可以基于GEC来校正具有错误的高速缓存行段。
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公开(公告)号：US20120185727A1
公开(公告)日：2012-07-19
申请号：US13007741
申请日：2011-01-17
申请人： Doe Hyun Yoon , Naveen Muralimanohar , Jichuan Chang , Parthasarathy Ranganathan , Norman Paul Jouppi
发明人： Doe Hyun Yoon , Naveen Muralimanohar , Jichuan Chang , Parthasarathy Ranganathan , Norman Paul Jouppi
CPC分类号： G06F11/1438 , G06F11/1076 , G06F11/2056 , G06F11/2094
摘要： Systems, methods, and computer-readable and executable instructions are provided for computing system reliability. A method for computing system reliability can include storing, on one of a plurality of devices, a checkpoint of a current state associated with the one of the plurality of devices. The method may further include storing the checkpoint in an erasure-code group across the plurality of devices.
摘要翻译： 提供系统，方法和计算机可读和可执行指令来计算系统的可靠性。 用于计算系统可靠性的方法可以包括在多个设备中的一个设备上存储与所述多个设备中的一个设备相关联的当前状态的检查点。 该方法还可以包括将检查点存储在多个设备中的擦除代码组中。
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公开(公告)号：US08108718B2
公开(公告)日：2012-01-31
申请号：US12618675
申请日：2009-11-13
IPC分类号： G06F11/00
CPC分类号： G06F11/1438
摘要： One embodiment is a method that performs a local checkpoint at a processing node in a massively parallel processing (MPP) system that executes a workload with a plurality of processing nodes. The local checkpoint is stored in local memory of the processing node. While the workload continues to execute, a global checkpoint is performed from the local checkpoint stored in the local memory.
摘要翻译： 一个实施例是在大量并行处理（MPP）系统中的处理节点处执行本地检查点的方法，其执行与多个处理节点的工作负载。 本地检查点存储在处理节点的本地存储器中。 当工作负载继续执行时，从本地存储器中存储的本地检查点执行全局检查点。
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公开(公告)号：US20110119525A1
公开(公告)日：2011-05-19
申请号：US12618675
申请日：2009-11-13
CPC分类号： G06F11/1438
摘要： One embodiment is a method that performs a local checkpoint at a processing node in a massively parallel processing (MPP) system that executes a workload with a plurality of processing nodes. The local checkpoint is stored in local memory of the processing node. While the workload continues to execute, a global checkpoint is performed from the local checkpoint stored in the local memory.
摘要翻译： 一个实施例是在大量并行处理（MPP）系统中的处理节点处执行本地检查点的方法，其执行与多个处理节点的工作负载。 本地检查点存储在处理节点的本地存储器中。 当工作负载继续执行时，从本地存储器中存储的本地检查点执行全局检查点。
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公开(公告)号：US20140247673A1
公开(公告)日：2014-09-04
申请号：US14349401
申请日：2011-10-28
申请人： Naveen Muralimanohar , Hans Boehm
发明人： Naveen Muralimanohar , Hans Boehm
IPC分类号： G11C11/4094 , G11C11/419
CPC分类号： G11C11/4094 , G11C7/1006 , G11C11/408 , G11C11/418 , G11C11/419 , G11C19/188 , G11C19/287
摘要： A shiftable memory employs row shifting to shift data along a row. The shiftable memory includes memory cells arranged as a plurality of rows and a plurality of columns. The shiftable memory further includes shift logic to shift data from an output of a first column to an input of a second column. The shifted data is provided by a memory cell of the first column in a selected row. The shifted data is received and stored by a memory cell in the selected row of the second column. The shift logic facilitates shifting data along the selected row.
摘要翻译： 可移位存储器使用行移位来沿着一行移位数据。 可移位存储器包括布置成多行和多列的存储单元。 可移位存储器还包括移位逻辑以将数据从第一列的输出移位到第二列的输入。 移位的数据由选定行中的第一列的存储单元提供。 移位的数据由第二列的所选行中的存储单元接收和存储。 移位逻辑有助于沿所选择的行移动数据。
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28.发明申请公开(公告)号：US20120268983A1
公开(公告)日：2012-10-25
申请号：US13092789
申请日：2011-04-22
IPC分类号： G11C11/00
CPC分类号： G11C29/028 , G11C13/0004 , G11C13/0035 , G11C13/0061 , G11C13/0069 , G11C29/021 , G11C29/50016 , G11C2013/0078
摘要： A memory device is provided. The memory device comprises an array of memory cells, each including a volume of material that can stably exhibit at least two different physical states that are each associated with a different data value, word lines that each interconnects a row of memory cells within the array of memory cells to a word-line driver, and bit lines that each interconnects a column of memory cells, through a bit-line driver, to a write driver that is controlled, during a WRITE operation, to write an input data value to an activated memory cell at the intersection of the column of memory cells and an activated row of memory cells by generating a current density within the memory cells that corresponds to retention/endurance characteristics of the memory cell dynamically assigned to the memory cell by a memory controller, operating system, or other control functionality.
摘要翻译： 提供存储器件。 存储器件包括存储器单元阵列，每个存储器单元包括能够稳定地呈现与不同数据值相关联的至少两种不同物理状态的材料体积，每条相互连接在该阵列内的一行存储器单元的字线 存储器单元到字线驱动器，以及位线，其每一个通过位线驱动器将存储器单元的列互连到在写操作期间被控制的写驱动器，以将输入数据值写入激活的 通过在存储器单元内产生对应于由存储器控制器动态地分配给存储器单元的存储器单元的保持/耐久特性的电流密度，在存储器单元列和激活的存储器单元行的交点处存储单元，操作 系统或其他控制功能。
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29.发明申请公开(公告)号：US20110246828A1
公开(公告)日：2011-10-06
申请号：US12751005
申请日：2010-03-31
CPC分类号： G06F11/1402 , G06F11/1438 , G06F11/1658 , G06F11/2025 , G06F11/2035 , G06F11/2097
摘要： A system and method is shown that includes a processor operatively connected to a memory, the processor to include a memory controller to control access to the memory. The system and method also includes a service processor, co-located on a common board and operatively connected to the processor and the memory, the service processor to include an additional memory controller to control access to the memory as part of a checkpoint regime.
摘要翻译： 示出了包括可操作地连接到存储器的处理器的系统和方法，所述处理器包括存储器控制器以控制对存储器的访问。 该系统和方法还包括服务处理器，共同位于公共板上并且可操作地连接到处理器和存储器，服务处理器包括附加存储器控制器以控制对作为检查点状态的一部分的对存储器的访问。
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公开(公告)号：US08516271B2
公开(公告)日：2013-08-20
申请号：US13046381
申请日：2011-03-11
CPC分类号： G06F12/0246 , G06F12/1441 , G06F12/1466 , G06F2212/225
摘要： Methods, apparatus and articles of manufacture to secure non-volatile memory regions are disclosed. An example method disclosed herein comprises associating a first key pair and a second key pair different than the first key pair with a process, using the first key pair to secure a first region of a non-volatile memory for the process, and using the second key pair to secure a second region of the non-volatile memory for the same process, the second region being different than the first region.
摘要翻译： 公开了用于安全非易失性存储器区域的方法，装置和制品。 本文公开的示例性方法包括：使用第一密钥对来将与第一密钥对不同的第一密钥对和第二密钥对与过程相关联，以使得用于该过程的非易失性存储器的第一区域被固定，并且使用第二密钥对 密钥对以固定用于相同处理的非易失性存储器的第二区域，第二区域不同于第一区域。
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