公开(公告)号：US06593660B2

公开(公告)日：2003-07-15

申请号：US09866937

申请日：2001-05-29

申请人： Leena P. Buchwalter ,  Barbara Luther ,  Paul D. Agnello ,  John P. Hummel ,  Terence Lawrence Kane ,  Dirk Karl Manger ,  Paul Stephen McLaughlin ,  Anthony Kendall Stamper ,  Yun Yu Wang

发明人： Leena P. Buchwalter ,  Barbara Luther ,  Paul D. Agnello ,  John P. Hummel ,  Terence Lawrence Kane ,  Dirk Karl Manger ,  Paul Stephen McLaughlin ,  Anthony Kendall Stamper ,  Yun Yu Wang

IPC分类号： H01L2348

CPC分类号： H01L21/3185 ,  H01L21/0445 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76834

摘要： The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure including a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.

摘要翻译： 本发明利用还原等离子体处理步骤来增强后续沉积的无机阻挡膜对铜线的粘附，或通过存在于诸如双镶嵌结构的半导体互连结构中。 在所述铜线或通孔与无机阻挡膜之间形成包括作为必需元素的Cu，Si和O的材料层的互连结构。

公开(公告)号：US06563131B1

公开(公告)日：2003-05-13

申请号：US09586501

申请日：2000-06-02

申请人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Christopher S. Putnam ,  Jed H. Rankin

发明人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Christopher S. Putnam ,  Jed H. Rankin

IPC分类号： H01L2906

CPC分类号： H01L29/78696 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/78654

摘要： Off-current is not compromised in a field effect transistor having a gate length less than 100 nanometers in length by maintaining the conduction channel width one-half to one-quarter of the gate length and locating the gate on at least two sides of the conduction channel and to thus create a full depletion device. Such a narrow conduction channel is achieved by forming a trough at minimum lithographic dimensions, forming sidewalls within the trough and etching the gate structure self-aligned with the sidewalls. The conduction channel is then epitaxially grown from the source structure in the trough such that the source, conduction channel and drain region are a unitary monocrystalline structure.

摘要翻译： 在栅极长度小于100纳米的场效应晶体管中，通过将导通沟道宽度保持为栅极长度的二分之一至四分之一，并将栅极定位在导电的至少两侧，不会损害截止电流 通道，从而创建一个完全耗尽的设备。 通过在最小光刻尺寸下形成槽，在槽内形成侧壁并蚀刻与侧壁自对准的栅极结构来实现这种窄导电沟道。 然后从槽中的源结构外延生长传导通道，使得源极，导电沟道和漏极区域是单一的单晶结构。

公开(公告)号：US5624869A

公开(公告)日：1997-04-29

申请号：US226923

申请日：1994-04-13

申请人： Paul D. Agnello ,  Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Matthew W. Copel ,  Francois M. d'Heurle ,  Qi-Zhong Hong

发明人： Paul D. Agnello ,  Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Matthew W. Copel ,  Francois M. d'Heurle ,  Qi-Zhong Hong

IPC分类号： H01L21/28 ,  H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L21/28518 ,  Y10S438/934

摘要： A method and a device directed to the same, for stabilizing cobalt di-silicide/single crystal silicon, amorphous silicon, polycrystalline silicon, germanide/crystalline germanium, polycrystalline germanium structures or other semiconductor material structures so that high temperature processing steps (above 750.degree. C.) do not degrade the structural quality of the cobalt di-silicide/silicon structure. The steps of the method include forming a di-silicide or germanide by either reacting cobalt with the substrate material and/or the codeposition of the di-silicide or germanide on a substrate, adding a selective element, either platinum or nitrogen, into the cobalt and forming the di-silicide or germanide by a standard annealing treatment. Alternatively, the cobalt di-silicide or cobalt germanide can be formed after the formation of the di-silicide or germanide respectively. As a result, the upper limit of the annealing temperature at which the di-silicide or germanide will structurally degrade is increased.

摘要翻译： 涉及其的方法和装置，用于稳定二硅化硅/单晶硅，非晶硅，多晶硅，锗化锗/结晶锗，多晶锗结构或其他半导体材料结构，使得高温处理步骤（高于750° C.）不会降低二硅化钴/硅结构的结构质量。 该方法的步骤包括通过使钴与基底材料反应和/或二硅化物或锗化物在基底上共沉积形成二硅化物或锗化物，向铂中添加铂或氮的选择性元素 并通过标准退火处理形成二硅化物或锗化物。 另外也可以分别在二硅化物或锗化物形成之后形成二硅化钴或锗化钴。 结果，二硅化物或锗化锗在结构上降解的退火温度的上限增加。

公开(公告)号：US5487783A

公开(公告)日：1996-01-30

申请号：US227752

申请日：1994-04-14

申请人： Paul D. Agnello ,  Thomas O. Sedgwick

发明人： Paul D. Agnello ,  Thomas O. Sedgwick

IPC分类号： C23C16/44 ,  C23C16/455 ,  C23C16/00

CPC分类号： C23C16/45561 ,  C23C16/4401 ,  C23C16/455

摘要： A method of maintaining an optimum pressure and purity level in a vessel having an inlet gas flow and an outlet gas flow during shutdown of the vessel that prevents imploding of the vessel when the inlet and outlet gas flows are discontinued. Gas from the vessel is directed to a containment portion in communication with the vessel. The pressure of the gas in the containment portion is monitored; the containment portion is backfilled with a purified inert gas when the monitored pressure drops to a predetermined lower level; and the containment portion is vented when the monitored pressure rises to a predetermined higher level. Apparatus for maintaining an optimum pressure and purity level in a vessel having an inlet gas flow and an outlet gas flow during shutdown of the vessel that prevents imploding of the vessel when the inlet and outlet gas flows are discontinued is also provided. The apparatus includes a containment portion adjacent to the vessel and in communication with the vessel for containing gas from the vessel, a back-pressure regulator and a conventional regulator for monitoring the pressure of the containment portion, a high-purity inert purge gas source in communication with the conventional regulator, adapted to backfill the containment portion with purified inert gas when the monitored pressure drops to a predetermined lower level, the back-pressure regulator adapted to vent the containment portion when the monitored pressure rises to a predetermined higher level.

摘要翻译： 在停机时，在容器关闭期间保持具有入口气流和出口气流的容器中的最佳压力和纯度水平的方法，其防止当入口气体和出口气体流过时容器内爆。 来自容器的气体被引导到与容器连通的容纳部分。 监测容纳部分中气体的压力; 当监测压力下降到预定的较低水平时，容纳部分用纯化的惰性气体回填; 并且当所监视的压力上升到预定的较高水平时，所述容纳部分被排出。 还提供了用于在容器停止期间具有入口气体流和出口气体流的容器中保持最佳压力和纯度水平的装置，其防止当入口和出口气体流动时中断容器的内泄。 该装置包括与容器相邻并与容器连通的容纳部分，用于容纳来自容器的气体，背压调节器和用于监测容纳部分的压力的常规调节器，高纯度惰性吹扫气体源 与常规调节器通信，适于当监测压力下降到预定的较低水平时用纯化的惰性气体回填容纳部分，背压调节器适于在监测的压力升高到预定的较高水平时排出容纳部分。

公开(公告)号：US5227330A

公开(公告)日：1993-07-13

申请号：US785731

申请日：1991-10-31

申请人： Paul D. Agnello ,  Tung-Sheng Kuan ,  Thomas O. Sedgwick

发明人： Paul D. Agnello ,  Tung-Sheng Kuan ,  Thomas O. Sedgwick

IPC分类号： C30B25/02 ,  H01L21/205

CPC分类号： C30B29/06 ,  C30B25/02 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02636

摘要： A system and method for growing low defect density epitaxial layers of Si on imperfectly cleaned Si surfaces by either selective or blanket deposition at low temperatures using the APCVD process wherein a first thin, e.g., 10 nm, layer of Si is grown on the surface from silane or disilane, followed by the growing of the remainder of the film from dichlorosilane (DCS) at the same low temperature, e.g., 550.degree. C. to 850.degree. C. The subsequent growth of the second layer with DCS over the first layer, especially if carried out immediately in the very same deposition system, will not introduce additional defects and may be coupled with high and controlled n-type doping which is not available in a silane-based system. Further, in order to achieve an optimal trade-off between the need for an inert ambience to promote silane reaction at low temperature and the need for a hydrogen ambience to prevent surface oxidation from inadvertant residual impurities, depositions are carried out in an ambience composed primarily of He but always containing some H.sub.2. Alternatively, instead of using He for H.sub.2 as the primary carrier gas when depositing Si from silane at low temperatures, DCS with a diborane additive may be used instead of silane in the normal hydrogen carrier. This modification permits DCS to be used in atmospheric pressure processes for Si deposition at low temperatures, which conventionally deposit Si selectively, to deposit blanket (non-selective) Si films over insulator and Si areas, and particularly such areas on a patterned wafer. Because the Si deposition rate is enhanced when diborane is added, significant non-selective deposition rates can occur down to 550.degree. C.

摘要翻译： 通过使用APCVD工艺在低温下通过选择性或覆盖沉积在不完全清洁的Si表面上生长Si的低缺陷密度外延层的系统和方法，其中在表面上生长第一薄例如10nm的Si层， 硅烷或乙硅烷，然后在相同的低温（例如550℃至850℃）下从二氯硅烷（DCS）中生长剩余的膜。随后在第一层上用DCS生长第二层， 特别是如果在相同的沉积系统中立即进行，则不会引入额外的缺陷，并且可能与在硅烷系统中不可用的高且受控的n型掺杂相结合。 此外，为了在惰性气氛促进低温下的硅烷反应的需要和氢气氛的需要之间实现最佳的权衡，以防止表面氧化从不经意的残留杂质，沉积在主要组成的环境中进行 他总是含有一些H2。 或者，代替在低温下从硅烷沉积Si时，He代替H 2作为主要载气，可以使用具有乙硼烷添加剂的DCS代替常规氢载体中的硅烷。 该修改允许DCS用于在低温下通常沉积Si的低温Si沉积的大气压力工艺中，以在绝缘体和Si区域上，特别是在图案化晶片上的这些区域上沉积覆盖层（非选择性）Si膜。 由于当加入乙硼烷时Si沉积速率增加，因此显着的非选择性沉积速率可能下降到550℃。

公开(公告)号：US20080135875A1

公开(公告)日：2008-06-12

申请号：US12031530

申请日：2008-02-14

申请人： Paul D. Agnello ,  Stephen W. Bedell ,  Robert H. Dennard ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Devendra K. Sadana

发明人： Paul D. Agnello ,  Stephen W. Bedell ,  Robert H. Dennard ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Devendra K. Sadana

IPC分类号： H01L21/84 ,  H01L27/12

CPC分类号： H01L21/324 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/66893 ,  H01L29/78603

摘要： Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.

摘要翻译： 提供形成基本上松弛和低缺陷的SGOI基底材料的热混合方法。 所述方法包括图形化步骤，其用于形成至少包含形成在Ge抗蚀扩散阻挡层顶上的SiGe岛的结构。 将SiGe层图案化成岛以这样的方式改变作用在每个岛边缘处的局部力，使得松弛力大于抵抗放松的力。 在图案化层的边缘处没有恢复力允许最终的SiGe膜比如果膜是连续的那样进一步松弛。

公开(公告)号：US06916729B2

公开(公告)日：2005-07-12

申请号：US10409516

申请日：2003-04-08

申请人： Sunfei Fang ,  Keith Kwong Hon Wong ,  Paul D. Agnello ,  Christian Lavoie ,  Lawrence A. Clevenger ,  Chester T. Dziobkowski ,  Richard J. Murphy ,  Patrick W. DeHaven ,  Nivo Rovedo ,  Hsiang-Jen Huang

发明人： Sunfei Fang ,  Keith Kwong Hon Wong ,  Paul D. Agnello ,  Christian Lavoie ,  Lawrence A. Clevenger ,  Chester T. Dziobkowski ,  Richard J. Murphy ,  Patrick W. DeHaven ,  Nivo Rovedo ,  Hsiang-Jen Huang

IPC分类号： H01L21/28 ,  H01L21/283 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518

摘要： A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.

摘要翻译： 在半导体器件上形成硅化物的方法包括在衬底的硅区域上沉积第一难熔金属层，在第一耐火金属层上沉积近贵金属层，以及在第二耐火金属层的近旁沉积第二难熔金属层， 贵金属层。 半导体器件在第一退火工艺中退火以形成邻接半导体器件的掺杂区域的硅化物层。 除去近贵金属层和第二难熔金属层的未反应部分。 该器件可以在任选的第二退火工艺中进行退火，以将硅化物层转换成低电阻相位硅化物材料。 通过本发明的实施例使结漏电和桥接最小化或消除，并且实现更平滑的硅化表面。

公开(公告)号：US06407436B1

公开(公告)日：2002-06-18

申请号：US09928965

申请日：2001-08-14

申请人： Paul D. Agnello ,  Peter I. Smeys

发明人： Paul D. Agnello ,  Peter I. Smeys

IPC分类号： H01L2976

CPC分类号： H01L29/6659 ,  H01L21/28105 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7836

摘要： A method for forming source/drain extensions with gate overlap. An oxide layer is formed on a semiconductor substrate and a gate structure on the semiconductor substrate. First, sidewall spacer regions are formed on sides of the gate structure. Second spacer regions are formed on sides of the sidewall spacer regions. Upper regions of the gate structure and the sidewall spacer regions are silicided. Portions of source and drain extension regions in the semiconductor substrate adjacent the gate structure are also silicided.

摘要翻译： 一种用栅极重叠形成源/漏扩展的方法。 在半导体衬底上形成氧化物层，在半导体衬底上形成栅极结构。 首先，在栅极结构的侧面上形成侧壁间隔区域。 第二间隔区域形成在侧壁间隔区域的侧面上。 栅极结构的上部区域和侧壁间隔区域被硅化。 与栅极结构相邻的半导体衬底中的源极和漏极延伸区域的部分也被硅化。

公开(公告)号：US06287913B1

公开(公告)日：2001-09-11

申请号：US09427506

申请日：1999-10-26

申请人： Paul D. Agnello ,  Bomy A. Chen ,  Scott W. Crowder ,  Ramachandra Divakaruni ,  Subramanian S. Iyer ,  Dennis Sinitsky

发明人： Paul D. Agnello ,  Bomy A. Chen ,  Scott W. Crowder ,  Ramachandra Divakaruni ,  Subramanian S. Iyer ,  Dennis Sinitsky

IPC分类号： H01L218242

CPC分类号： H01L27/10861 ,  H01L21/823443 ,  H01L21/82345 ,  H01L27/10873 ,  H01L27/10894

摘要： A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory region and the logic region, removing the protective layer over the logic region to expose the substrate, and forming the logic device in the logic region. Cobalt or titanium metal is applied over all horizontal surfaces in the logic region and annealed, forming a salicide where the metal rests over silicon or polysilicon regions, and any unreacted metal is removed. An uppermost nitride layer is then applied over both the memory and logic regions and is then covered with a filler in the logic region. Chip structures resulting from various embodiments of the process are also disclosed.

摘要翻译： 在同一半导体芯片上制造紧凑型存储器和高性能逻辑的工艺。 该过程包括在存储器区域中形成存储器件，在存储区域和逻辑区域两者之间形成间隔氮化物层和保护层，去除逻辑区域上的保护层以暴露衬底，以及形成逻辑器件 逻辑区域。 将钴或钛金属施加在逻辑区域的所有水平表面上并退火，形成硅化物，其中金属沉积在硅或多晶硅区域上，并且任何未反应的金属被去除。 然后将最上面的氮化物层施加在存储器和逻辑区域两者上，然后在逻辑区域中用填料覆盖。 还公开了由该方法的各种实施方案产生的芯片结构。

公开(公告)号：US06274446B1

公开(公告)日：2001-08-14

申请号：US09407632

申请日：1999-09-28

申请人： Paul D. Agnello ,  Peter I. Smeys

发明人： Paul D. Agnello ,  Peter I. Smeys

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/28105 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7836

摘要： A method for forming source/drain extensions with gate overlap. An oxide layer is formed on a semiconductor substrate and a gate structure on the semiconductor substrate. First, sidewall spacer regions are formed on sides of the gate structure. Second spacer regions are formed on sides of the sidewall spacer regions. Upper regions of the gate structure and the sidewall spacer regions are silicided. Portions of source and drain extension regions in the semiconductor substrate adjacent the gate structure are also silicided.

摘要翻译： 一种用栅极重叠形成源/漏扩展的方法。 在半导体衬底上形成氧化物层，在半导体衬底上形成栅极结构。 首先，在栅极结构的侧面上形成侧壁间隔区域。 第二间隔区域形成在侧壁间隔区域的侧面上。 栅极结构的上部区域和侧壁间隔区域被硅化。 与栅极结构相邻的半导体衬底中的源极和漏极延伸区域的部分也被硅化。