公开(公告)号：US20240178277A1

公开(公告)日：2024-05-30

申请号：US18523734

申请日：2023-11-29

Applicant: Renesas Electronics Corporation

Inventor： Katsumi EIKYU ,  Ryota KURODA ,  Hitoshi MATSUURA ,  Sho NAKANISHI

IPC: H01L29/08 ,  H01L21/265 ,  H01L21/266 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/0804 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/0696 ,  H01L29/41708 ,  H01L29/66348 ,  H01L29/7397

Abstract: A semiconductor substrate includes a plurality of emitter formation regions separated from each other in a Y direction between a pair of trenches, and a separation region located between the emitter formation regions. A p-type base region is formed in the semiconductor substrate of each of the emitter formation regions and the separation region. An n-type impurity region is formed in the base region of each emitter formation region. The impurity region is also formed in the base region at a position in contact with the pair of trenches in the separation region.

公开(公告)号：US20230369414A1

公开(公告)日：2023-11-16

申请号：US18358474

申请日：2023-07-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Nobuo MACHIDA

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L29/66734 ,  H01L29/7813

Abstract: Semiconductor device has a cell region and a peripheral region, and has a drift layer, a trench, an gate dielectric film on an inner wall of the trench, a gate electrode, and a p-type first semiconductor region below the trench in the cell region on a semiconductor substrate. Further, in the peripheral region on the semiconductor substrate, p-type second semiconductor region is formed in the same layer as the p-type first semiconductor region. a width of the p-type first semiconductor region and a width of the p-type second semiconductor region are different.

公开(公告)号：US20230112550A1

公开(公告)日：2023-04-13

申请号：US17886073

申请日：2022-08-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuta NABUCHI ,  Hiroshi YANAGIGAWA ,  Katsumi EIKYU ,  Atsushi SAKAI

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/266

Abstract: A semiconductor device and a method of manufacturing the same capable of ensuring a sufficient breakdown voltage near a terminal end portion of a cell portion are provided. The cell portion includes a first cell column region and a second cell column region adjacent to each other, and a first cell trench gate and a second cell trench gate arranged between the first cell column region and the second cell column region. An outer peripheral portion includes an outer peripheral trench gate connected to an end portion of each of the first cell trench gate and the second cell trench gate, and a first outer peripheral column region arranged on the cell portion side with respect to the outer peripheral trench gate and extended across the first cell trench gate and the second cell trench gate in plan view.

公开(公告)号：US20190393169A1

公开(公告)日：2019-12-26

申请号：US16444823

申请日：2019-06-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsumi EIKYU ,  Fumihito OTA ,  Takashi IPPOSHI

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/522

Abstract: The semiconductor device SD1a includes a first wiring M2 and a second wiring M3. The semiconductor device includes a first conductor pattern DM, a first via V2 in contact with the first wiring M2 and the second wiring M3, and a second via DV1, DV2, DV3, DV4 in contact with the first conductor pattern DM and the second wiring M3. In plan view, the distance between the second via DV1 closest to the corner portion CI of the second wire M3 and the corner portion CI is shorter than the distance between the first via V2 and the corner portion CI, and the distance between the second vias adjacent to each other is shorter than the distance between the second via DV3 closest to the first via V2 and the first via V2.

公开(公告)号：US20190237577A1

公开(公告)日：2019-08-01

申请号：US16223839

申请日：2018-12-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Koichi ARAI ,  Kenichi HISADA ,  Yasunori YAMASHITA ,  Satoshi EGUCHI ,  Hironobu MIYAMOTO ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/36 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7813 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02634 ,  H01L21/0274 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/66068

Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

公开(公告)号：US20190198663A1

公开(公告)日：2019-06-27

申请号：US16192480

申请日：2018-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Satoshi EGUCHI ,  Nobuo MACHIDA ,  Koichi ARAI ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Yasunori YAMASHITA

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/0865 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66734

Abstract: To improve characteristics of a semiconductor device. A first p-type semiconductor region having an impurity of a conductivity type opposite from that of a drift layer is arranged in the drift layer below a trench, and a second p-type semiconductor region is further arranged that is spaced at a distance from a region where the trench is formed as seen from above and that has the impurity of the conductivity type opposite from that of the drift layer. The second p-type semiconductor region is configured by a plurality of regions arranged at a space in a Y direction (depth direction in the drawings). Thus, it is possible to reduce the specific on-resistance while maintaining the breakdown voltage of the gate insulating film by providing the first and second p-type semiconductor regions and further by arranging the second p-type semiconductor region spaced by the space.

公开(公告)号：US20180026134A1

公开(公告)日：2018-01-25

申请号：US15649984

申请日：2017-07-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsumi EIKYU ,  Atsushi SAKAI

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L21/28 ,  H01L29/08

CPC classification number: H01L29/7835 ,  H01L21/28061 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/402 ,  H01L29/42312 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/78624

Abstract: In an LDMOS having an element isolation region of an STI structure, there is prevented an occurrence of insulation breakdown which might be caused when electrons generated in a semiconductor substrate near an edge portion of a bottom face of the element isolation region are poured into a gate electrode. Immediately over an upper surface of an offset region adjacent to the element isolation region embedded in a main surface of the semiconductor substrate between a source region and a drain region, there is provided a trench penetrating a silicon film forming the gate electrode. As a consequence, the silicon film and a metal film for filling the trench form the gate electrode.

公开(公告)号：US20170077166A1

公开(公告)日：2017-03-16

申请号：US15218257

申请日：2016-07-25

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya KITAMORI ,  Kyoji YAMASAKI ,  Katsumi EIKYU

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14609 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14641

Abstract: Image sensor devices of related art have a problem that an auto-focus accuracy deteriorates due to crosstalk of electrons between a plurality of photodiodes formed below one microlens. According to one embodiment, at least some of a plurality of pixels in an image sensor device include: first and second photoelectric conversion elements (PD_L, PD_R) that are formed on a semiconductor substrate below one microlens (45); and a potential barrier (34) that inhibits transfer of electric charges between at least a part of a lower region of the first photoelectric conversion element (PD_L) and at least a part of a lower region of the second photoelectric conversion element (PD_R) in a depth direction of the semiconductor substrate.

Abstract translation: 相关技术的图像传感器装置存在由于在一个微透镜之下形成的多个光电二极管之间的电子的串扰而导致自动聚焦精度劣化的问题。 根据一个实施例，图像传感器装置中的多个像素中的至少一些像素包括：形成在低于一微透镜（45）的半导体衬底上的第一和第二光电转换元件（PD_L，PD_R）; 以及阻止在第一光电转换元件（PD_L）的下部区域的至少一部分与第二光电转换元件（PD_R）的下部区域的至少一部分之间的电荷的转移的势垒（34） 半导体衬底的深度方向。