公开(公告)号：US09905429B2

公开(公告)日：2018-02-27

申请号：US15473568

申请日：2017-03-29

Applicant: Renesas Electronics Corporation

Inventor： Tatsuyoshi Mihara ,  Masaaki Shinohara

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11568 ,  H01L27/11573

CPC classification number: H01L21/28282 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

Abstract: The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, a first insulation film, a conductive film, a silicon-containing second insulation film, and a third film formed of silicon are sequentially formed at the surface of a control gate electrode. Then, the third film is etched back to leave the third film at the side surface of the control gate electrode via the first insulation film, the conductive film, and the second insulation film, thereby to form a spacer. Then, the conductive film is etched back to form a memory gate electrode formed of the conductive film between the spacer and the control gate electrode, and between the spacer and the semiconductor substrate.

公开(公告)号：US09837427B2

公开(公告)日：2017-12-05

申请号：US15412465

申请日：2017-01-23

Applicant: Renesas Electronics Corporation

Inventor： Masaaki Shinohara

IPC: H01L21/8234 ,  H01L21/266 ,  H01L27/11568 ,  H01L21/311 ,  H01L21/265 ,  H01L29/66 ,  H01L21/02 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11573 ,  H01L21/28 ,  H01L29/792 ,  H01L29/423 ,  G11C16/04

CPC classification number: H01L27/11568 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66833 ,  H01L29/792

Abstract: Deterioration in reliability is prevented regarding a semiconductor device. The deterioration is caused when an insulating film for formation of a sidewall is embedded between gate electrodes at the time of forming sidewalls having two kinds of different widths on a substrate. A sidewall-shaped silicon oxide film is formed over each sidewall of a gate electrode of a low breakdown voltage MISFET and a pattern including a control gate electrode and a memory gate electrode. Then, a silicon oxide film beside the gate electrode is removed, and a silicon oxide film is formed on a semiconductor substrate, and then etchback is performed. Accordingly, a sidewall, formed of a silicon nitride film and the silicon oxide film, is formed beside the gate electrode, and a sidewall, formed of the silicon nitride film and the silicon oxide films, is formed beside the pattern.

公开(公告)号：US09679908B2

公开(公告)日：2017-06-13

申请号：US15062504

申请日：2016-03-07

Applicant: Renesas Electronics Corporation

Inventor： Masaaki Shinohara

IPC: H01L21/336 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/792 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/28282 ,  H01L21/3212 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/42344 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

Abstract: Provided is a semiconductor device having improved performance. In a semiconductor substrate located in a memory cell region, a memory cell of a nonvolatile memory is formed while, in the semiconductor substrate located in a peripheral circuit region, a MISFET is formed. At this time, over the semiconductor substrate located in the memory cell region, a control gate electrode and a memory gate electrode each for the memory cell are formed first. Then, an insulating film is formed so as to cover the control gate electrode and the memory gate electrode. Subsequently, the upper surface of the insulating film is polished to be planarized. Thereafter, a conductive film for the gate electrode of the MISFET is formed and then patterned to form a gate electrode or a dummy gate electrode for the MISFET in the peripheral circuit region.

公开(公告)号：US09553121B2

公开(公告)日：2017-01-24

申请号：US14835284

申请日：2015-08-25

Applicant: Renesas Electronics Corporation

Inventor： Hiroaki Sekikawa ,  Hidenori Sato ,  Yotaro Goto ,  Takuya Maruyama ,  Masaaki Shinohara

IPC: H01L21/4763 ,  H01L27/146 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/66 ,  H01L23/532

CPC classification number: H01L27/14636 ,  H01L21/31051 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76877 ,  H01L22/30 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/14603 ,  H01L27/14687 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A connection portion connects a copper-based first wiring layer with a copper-based second wiring layer arranged on the upper side of a first diffusion barrier film. The first diffusion barrier film includes a first opening region formed in a semiconductor circuit region that is a partial region in a two-dimensional view and a second opening region formed as an opening region different from the first opening region in a two-dimensional view. The opening regions are formed in a region different from an opening region formed to allow the connection portion to pass through the first diffusion barrier film. A mark wiring layer is arranged immediately above the second opening region as the same layer as the second wiring layer. A second diffusion barrier film is arranged in contact with the upper surface of the mark wiring layer.

Abstract translation: 连接部分将铜基第一布线层与布置在第一扩散阻挡膜的上侧上的铜基第二布线层连接。 第一扩散阻挡膜包括在二维视图中形成在作为二维视图的局部区域的半导体电路区域中形成的第一开口区域和形成为与二维视图中的第一开口区域不同的开口区域的第二开口区域。 开口区域形成在与形成为允许连接部分穿过第一扩散阻挡膜的开口区域不同的区域中。 标记布线层设置在与第二布线层相同的层的正上方的第二开口区域的正上方。 第二扩散阻挡膜布置成与标记布线层的上表面接触。

公开(公告)号：US09318500B2

公开(公告)日：2016-04-19

申请号：US14085825

申请日：2013-11-21

Applicant: Renesas Electronics Corporation

Inventor： Masaaki Shinohara

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/792

CPC classification number: H01L21/28282 ,  H01L21/3212 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/42344 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

Abstract: Provided is a semiconductor device having improved performance. In a semiconductor substrate located in a memory cell region, a memory cell of a nonvolatile memory is formed while, in the semiconductor substrate located in a peripheral circuit region, a MISFET is formed. At this time, over the semiconductor substrate located in the memory cell region, a control gate electrode and a memory gate electrode each for the memory cell are formed first. Then, an insulating film is formed so as to cover the control gate electrode and the memory gate electrode. Subsequently, the upper surface of the insulating film is polished to be planarized. Thereafter, a conductive film for the gate electrode of the MISFET is formed and then patterned to form a gate electrode or a dummy gate electrode for the MISFET in the peripheral circuit region.

Abstract translation: 提供了具有改进的性能的半导体器件。 在位于存储单元区域中的半导体衬底中，形成非易失性存储器的存储单元，同时形成位于外围电路区域中的半导体衬底中的MISFET。 此时，首先在位于存储单元区域的半导体基板上形成各自用于存储单元的控制栅电极和存储栅电极。 然后，形成绝缘膜以覆盖控制栅电极和存储栅电极。 随后，绝缘膜的上表面被抛光以平坦化。 此后，形成用于MISFET的栅电极的导电膜，然后将其图案化以在外围电路区域中形成用于MISFET的栅电极或伪栅电极。

公开(公告)号：US09305824B2

公开(公告)日：2016-04-05

申请号：US14738846

申请日：2015-06-13

Applicant: Renesas Electronics Corporation

Inventor： Masaaki Shinohara ,  Satoshi Iida

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L21/76224 ,  H01L21/308 ,  H01L21/76205 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833

Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film.The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

公开(公告)号：US20140377889A1

公开(公告)日：2014-12-25

申请号：US14304951

申请日：2014-06-15

Applicant: Renesas Electronics Corporation

Inventor： Hiraku Chakihara ,  Akihiro Nakae ,  Masaaki Shinohara ,  Yasushi Ishii

IPC: H01L21/66 ,  H01L21/033

CPC classification number: H01L22/12 ,  H01L23/544 ,  H01L27/11573 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device manufacturing method which eliminates the possibility that when a film is processed several times, a thin photoresist film is made over a pattern used as an alignment mark, etc. and the pattern is exposed from the photoresist film and removed in a processing step, in order to improve the reliability of a semiconductor device. Patterns used as alignment marks, etc. are linear trenches as openings in a conductive film made over a semiconductor substrate, thereby preventing the photoresist film over the conductive film from flowing toward the openings in the conductive film.

Abstract translation: 一种半导体器件制造方法，其消除了当膜被加工数次时，在用作对准标记等的图案上形成薄的光致抗蚀剂膜，并且图案从光致抗蚀剂膜暴露并在处理步骤中去除 ，以提高半导体器件的可靠性。 用作对准标记等的图案是在半导体衬底上形成的导电膜中的开口的线性沟槽，从而防止导电膜上的光致抗蚀剂膜朝向导电膜中的开口流动。

公开(公告)号：US20130264644A1

公开(公告)日：2013-10-10

申请号：US13859297

申请日：2013-04-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takaaki Tsunomura ,  Yoshiki Yamamoto ,  Masaaki Shinohara ,  Toshiaki Iwamatsu ,  Hidekazu Oda

IPC: H01L27/12 ,  H01L29/66

CPC classification number: H01L27/1203 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/1207 ,  H01L29/41783 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

Abstract translation: 在其上表面上形成有SOI区域和体硅区域的半导体衬底上，在形成于SOI区域的MOSFET的源极和漏极区域中形成外延层，在源极和漏极区域中不形成外延层 在体硅区域形成MOSFET。 通过用氮化硅膜覆盖外延层的端部，即使当通过从外延层上方注入离子形成扩散层时，也可以防止杂质离子注入到硅层的下表面。