公开(公告)号：US20180175136A1

公开(公告)日：2018-06-21

申请号：US15888594

申请日：2018-02-05

Applicant: Renesas Electronics Corporation

Inventor： Kenichiro HIJIOKA ,  Akira TANABE ,  Yoshihiro HAYASHI

IPC: H01L49/02 ,  H01F41/04 ,  H01F17/00 ,  H01F27/34

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F27/34 ,  H01F41/041 ,  H01F2017/002 ,  H01F2017/004 ,  H01F2017/0086 ,  Y10T29/4902 ,  Y10T29/49071

Abstract: An inductor element is formed in a multiple layer lead structure including a lead, an insulative layer that insulates leads above and below, and a via provided in the insulative layer and connecting leads above and below wherein lead layers are multiply laminated layers, characterized in that: at least a portion of at least a pair of vertically adjacent leads are coiled leads; the coiled leads are connected in series, wherein current directions of vertically adjacent coiled leads are the same by a via provided on an end portion thereof, and form a serial inductance; and an inter-lead capacitance of the vertically adjacent coiled leads is larger than an inter-lead capacitance between other coiled leads formed in the same lead layer.

公开(公告)号：US20160240625A1

公开(公告)日：2016-08-18

申请号：US15139563

申请日：2016-04-27

Applicant: Renesas Electronics Corporation

Inventor： Naoya INOUE ,  Kishou KANEKO ,  Yoshihiro HAYASHI

IPC: H01L29/423 ,  H01L23/522 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/42384 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02565 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a semiconductor device having the semiconductor element that uses a wire in a wiring layer as a gate electrode and has a gate insulation film in an identical layer to the diffusion prevention film. A first wire and a gate electrode are embedded into the surface layer of an insulation layer comprising a first wiring layer. A diffusion prevention film is formed between the first wiring layer and a second wiring layer. A gate insulation film is formed by: forming a recess over the upper face of the diffusion prevention film in the region overlapping with the gate electrode and around the region; and thinning the part.

Abstract translation: 本发明可以降低半导体元件的导通电阻，而不会妨碍具有使用布线层中的导线的半导体元件作为栅电极的半导体器件中的扩散防止膜的功能，并具有栅极绝缘膜 在与扩散防止膜相同的层中。 第一导线和栅电极嵌入到包括第一布线层的绝缘层的表面层中。 在第一布线层和第二布线层之间形成扩散防止膜。 栅极绝缘膜通过以下方式形成：在与栅电极重叠的区域和区域周围形成在扩散防止膜的上表面上的凹部; 并使部件变薄。

公开(公告)号：US20150056762A1

公开(公告)日：2015-02-26

申请号：US14527019

申请日：2014-10-29

Applicant: Renesas Electronics Corporation

Inventor： Naoya INOUE ,  Kishou KANEKO ,  Yoshihiro HAYASHI

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L29/42384 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02565 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a semiconductor device having the semiconductor element that uses a wire in a wiring layer as a gate electrode and has a gate insulation film in an identical layer to the diffusion prevention film. A first wire and a gate electrode are embedded into the surface layer of an insulation layer comprising a first wiring layer. A diffusion prevention film is formed between the first wiring layer and a second wiring layer. A gate insulation film is formed by: forming a recess over the upper face of the diffusion prevention film in the region overlapping with the gate electrode and around the region; and thinning the part.

Abstract translation: 本发明可以降低半导体元件的导通电阻，而不会妨碍具有使用布线层中的导线的半导体元件作为栅电极的半导体器件中的扩散防止膜的功能，并具有栅极绝缘膜 在与扩散防止膜相同的层中。 第一导线和栅电极嵌入到包括第一布线层的绝缘层的表面层中。 在第一布线层和第二布线层之间形成扩散防止膜。 栅极绝缘膜通过以下方式形成：在与栅电极重叠的区域和区域周围形成在扩散防止膜的上表面上的凹部; 并使部件变薄。

公开(公告)号：US20140295657A1

公开(公告)日：2014-10-02

申请号：US14300836

申请日：2014-06-10

Applicant: Renesas Electronics Corporation

Inventor： Naoya INOUE ,  Kishou KANEKO ,  Yoshihiro HAYASHI

IPC: H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/76879 ,  H01L23/522 ,  H01L23/53223 ,  H01L23/5329 ,  H01L28/60 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a semiconductor device provided with an active element in a multilayer interconnect layer and decreased in a chip area. A second interconnect layer is provided over a first interconnect layer. A first interlayer insulating layer is provided in the first interconnect layer. A semiconductor layer is provided in a second interconnect layer and in contact with the first interlayer insulating layer. A gate insulating film is provided over the semiconductor layer. A gate electrode is provided over the gate insulating film. At least two first vias are provided in the first interconnect layer and in contact by way of upper ends thereof with the semiconductor layer.

Abstract translation: 公开了一种半导体器件，其在多层互连层中设置有源元件并且在芯片面积上减小。 在第一互连层上提供第二互连层。 第一层间绝缘层设置在第一互连层中。 半导体层设置在第二互连层中并与第一层间绝缘层接触。 在半导体层上设置栅极绝缘膜。 在栅绝缘膜上设置栅电极。 至少两个第一通孔设置在第一互连层中并且通过其上端与半导体层接触。

公开(公告)号：US20130299952A1

公开(公告)日：2013-11-14

申请号：US13887668

申请日：2013-05-06

Applicant: Renesas Electronics Corporation

Inventor： Hironori YAMAMOTO ,  Fuminori ITO ,  Yoshihiro HAYASHI

IPC: H01L21/02 ,  H01L29/02

CPC classification number: H01L29/0657 ,  H01B3/46 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/7682 ,  H01L21/76825 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/535 ,  H01L27/228 ,  H01L29/02 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The deposition rate of a porous insulation film is increased, and the film strength of the porous insulation film is improved. Two or more organic siloxane raw materials each having a cyclic SiO structure as a main skeleton thereof, and having mutually different structures, are vaporized, and transported with a carrier gas to a reactor (chamber), and an oxidant gas including an oxygen atom is added thereto. Thus, a porous insulation film is formed by a plasma CVD (Chemical Vapor Deposition) method or a plasma polymerization method in the reactor (chamber). In the step, the ratio of the flow rate of the added oxidant gas to the flow rate of the carrier gas is more than 0 and 0.08 or less.

Abstract translation: 多孔绝缘膜的沉积速率提高，多孔绝缘膜的膜强度提高。 两种以上的具有环状SiO结构作为主要骨架并且具有相互不同结构的有机硅氧烷原料被蒸发并用载气输送到反应器（室），并且包含氧原子的氧化剂气体是 加入。 因此，在反应器（室）中通过等离子体CVD（化学气相沉积）法或等离子体聚合法形成多孔绝缘膜。 在该步骤中，添加的氧化剂气体的流量与载气的流量的比率大于0和0.08以下。

公开(公告)号：US20130181221A1

公开(公告)日：2013-07-18

申请号：US13710209

申请日：2012-12-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kishou KANEKO ,  Hiroshi SUNAMURA ,  Yoshihiro HAYASHI

IPC: H01L29/786 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/786 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/12 ,  H01L27/1259 ,  H01L28/20 ,  H01L29/66742 ,  H01L2924/0002 ,  H03K19/00 ,  H01L2924/00

Abstract: A circuit including an inverter is provided for a wiring layer.A semiconductor device is provided with a wiring layer circuit which is formed over an insulating film and includes at least one inverter element. The inverter is provided with a first transistor element and a resistance element which is connected to the first transistor via a connection node. The first transistor element is provided with a gate electrode which is embedded in an interlayer insulating film including the insulating film, a gate insulating film which is formed over the interlayer insulating film and the gate electrode, and a first semiconductor layer which is formed over the gate insulating film between a source electrode and a drain electrode. The resistance element is provided with a second semiconductor layer which functions as a resistance. The first semiconductor layer and the second semiconductor layer are formed in the same layer.

Abstract translation: 为布线层设置包括逆变器的电路。 半导体器件设置有形成在绝缘膜上并且包括至少一个反相器元件的布线层电路。 逆变器设置有第一晶体管元件和电阻元件，其经由连接节点连接到第一晶体管。 第一晶体管元件设置有嵌入在包括绝缘膜的层间绝缘膜中的栅极电极，形成在层间绝缘膜和栅电极之上的栅极绝缘膜，以及形成在第一半导体层上的第一半导体层 源电极和漏电极之间的栅极绝缘膜。 电阻元件设置有用作电阻的第二半导体层。 第一半导体层和第二半导体层形成在同一层中。

公开(公告)号：US20130178061A1

公开(公告)日：2013-07-11

申请号：US13715280

申请日：2012-12-14

Applicant: Renesas Electronics Corporation

Inventor： Hironori YAMAMOTO ,  Fuminori ITO ,  Yoshihiro HAYASHI

IPC: H01L21/3105 ,  H01L21/3205

CPC classification number: H01L21/3105 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/3205 ,  H01L21/76807 ,  H01L21/76826

Abstract: First, a porous insulating film 120 is formed using an organic silica raw material containing a hydrocarbon group. The hydrocarbon group contains, for example, an unsaturated carbon compound, but may contain a saturated carbon compound. The skeleton of the organic silica is, for example, cyclic organic silica. Next, the surface of the porous insulating film 120 is subjected to plasma processing by using a processing gas containing an inactive gas and a reducing gas. Subsequently, in the porous insulating film 120, a wiring trench 123 is formed and is embedded with wiring 124.

Abstract translation: 首先，使用含有烃基的有机二氧化硅原料形成多孔绝缘膜120。 烃基含有例如不饱和碳化合物，但可以含有饱和碳化合物。 有机二氧化硅的骨架是例如环状有机二氧化硅。 接下来，通过使用含有惰性气体和还原气体的处理气体对多孔绝缘膜120的表面进行等离子体处理。 随后，在多孔绝缘膜120中形成布线沟槽123并嵌入布线124。

公开(公告)号：US20130168817A1

公开(公告)日：2013-07-04

申请号：US13670138

申请日：2012-11-06

Applicant: Renesas Electronics Corporation

Inventor： Jun KAWAHARA ,  Naoya INOUE ,  Naoya FURUTAKE ,  Yoshihiro HAYASHI

IPC: H01L49/02

CPC classification number: H01L28/24 ,  H01L23/5228 ,  H01L27/0629 ,  H01L27/0802 ,  H01L2924/0002 ,  Y10S257/904 ,  H01L2924/00

Abstract: A semiconductor device includes a first insulating layer (interlayer insulating layer), a resistive element that is disposed over the first insulating layer (interlayer insulating layer) and at least a surface layer of which is a TaSiN layer, and an interlayer insulating layer disposed over the first insulating layer (interlayer insulating layer) and the resistive element. Multiple via plugs having ends coupled to the TaSiN layer are disposed in the interlayer insulating layer.

Abstract translation: 半导体器件包括：第一绝缘层（层间绝缘层），设置在第一绝缘层（层间绝缘层）上的电阻元件，至少其表面层为TaSiN层;以及层间绝缘层， 第一绝缘层（层间绝缘层）和电阻元件。 在层间绝缘层中设置多个具有与TaSiN层结合的端子的通孔塞。

公开(公告)号：US20130105772A1

公开(公告)日：2013-05-02

申请号：US13659461

申请日：2012-10-24

Applicant: Renesas Electronics Corporation

Inventor： Jun KAWAHARA ,  Yoshihiro HAYASHI

IPC: C08G77/20 ,  H01L51/30 ,  H01L51/05

CPC classification number: H01L51/0094 ,  C08G77/60 ,  C08G77/62 ,  H01L51/004 ,  H01L51/0079 ,  H01L51/0541 ,  H01L51/0545

Abstract: A semiconductor device containing a novel cyclosiloxane polymer showing electroconductivity or semiconductivity has a charge transport layer comprising a plasma polymer containing structural units (A) each having a transition metal as a central metal and structural units (B) each situated between structural units (A) adjacent to each other and having a cyclosiloxane skeleton. The charge transport layer is formed by plasma polymerization of an organic metal compound having the transition metal as the central metal and the cyclosiloxane compound in a reactor.

Abstract translation: 包含显示导电性或半导电性的新型环硅氧烷聚合物的半导体器件具有电荷输送层，其包含含有各自具有作为中心金属的过渡金属的结构单元（A）的等离子体聚合物和各自位于结构单元（A）之间的结构单元（B） 相邻并具有环硅氧烷骨架。 电荷输送层通过在反应器中等离子体化具有作为中心金属的过渡金属和环硅氧烷化合物的有机金属化合物形成。