中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

63 records (took 0.031 seconds)

    METHOD OF CONTROLLING EMBEDDED MATERIAL/GATE PROXIMITY
    21.
    发明申请
    METHOD OF CONTROLLING EMBEDDED MATERIAL/GATE PROXIMITY 有权
    控制嵌入材料/栅格近似的方法

    公开(公告)号：US20090280579A1

    公开(公告)日：2009-11-12

    申请号：US12119196

    申请日：2008-05-12

    Applicant: Rohit Pal ,  David E. Brown ,  Alok Vaid ,  Kevin Lensing

    Inventor： Rohit Pal ,  David E. Brown ,  Alok Vaid ,  Kevin Lensing

    IPC: H01L21/66

    CPC classification number: H01L29/7848 ,  H01L22/12 ,  H01L22/20 ,  H01L29/66636 ,  H01L29/78

    Abstract: A method that includes forming a gate of a semiconductor device on a substrate and forming a recess for an embedded silicon-straining material in source and drain regions for the gate. In this method, a proximity value, which is defined as a distance between the gate and a closest edge of the recess, is controlled by controlling formation of an oxide layer provided beneath the gate. The method can also include feedforward control of process steps in the formation of the recess based upon values measured during the formation of the recess. The method can also apply feedback control to adjust a subsequent recess formation process performed on a subsequent semiconductor device based on the comparison between a measured proximity value and a target proximity value to decrease a difference between a proximity value of the subsequent semiconductor device and the target proximity value.

    Abstract translation: 一种方法，包括在衬底上形成半导体器件的栅极，并在栅极的源极和漏极区域中形成嵌入的硅应变材料的凹部。 在该方法中，通过控制形成在栅极下方的氧化物层来控制被定义为栅极和凹部的最近边缘之间的距离的接近值。 该方法还可以包括基于在形成凹部期间测量的值来形成凹部中的工艺步骤的前馈控制。 该方法还可以基于测量的接近度值和目标接近值之间的比较来应用反馈控制来调整对随后的半导体器件执行的随后的凹陷形成处理，以减小随后的半导体器件的接近值与目标之间的差异 接近值。

    STRESS ENHANCED MOS TRANSISTOR AND METHODS FOR ITS FABRICATION
    22.
    发明申请
    STRESS ENHANCED MOS TRANSISTOR AND METHODS FOR ITS FABRICATION 有权
    应力增强MOS晶体管及其制造方法

    公开(公告)号：US20080119031A1

    公开(公告)日：2008-05-22

    申请号：US11562209

    申请日：2006-11-21

    Applicant: Rohit Pal ,  Igor Peidous ,  David Brown

    Inventor： Rohit Pal ,  Igor Peidous ,  David Brown

    IPC: H01L21/20 ,  H01L21/36 ,  H01L31/20

    CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66636

    Abstract: A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode overlying and defining a channel region in a monocrystalline semiconductor substrate. A trench having a side surface facing the channel region is etched into the monocrystalline semiconductor substrate adjacent the channel region. The trench is filled with a second monocrystalline semiconductor material having a first concentration of a substitutional atom and with a third monocrystalline semiconductor material having a second concentration of the substitutional atom. The second monocrystalline semiconductor material is epitaxially grown to have a wall thickness along the side surface sufficient to exert a greater stress on the channel region than the stress that would be exerted by a monocrystalline semiconductor material having the second concentration if the trench was filled by the third monocrystalline material alone.

    Abstract translation: 提供了一种应力增强型MOS晶体管及其制造方法。 在一个实施例中，该方法包括形成覆盖并限定单晶半导体衬底中的沟道区的栅电极。 具有面向通道区域的侧表面的沟槽被蚀刻到与沟道区域相邻的单晶半导体衬底中。 沟槽填充有具有第一浓度的取代原子的第二单晶半导体材料和具有第二浓度取代原子的第三单晶半导体材料。 第二单晶半导体材料被外延生长以具有沿着侧表面的壁厚，足以在沟道区域施加比由具有第二浓度的单晶半导体材料施加的应力更大的应力，如果沟槽由 第三单晶材料。

    Formation of a channel semiconductor alloy by a nitride hard mask layer and an oxide mask
    24.
    发明授权
    Formation of a channel semiconductor alloy by a nitride hard mask layer and an oxide mask 有权
    通过氮化物硬掩模层和氧化物掩模形成沟道半导体合金

    公开(公告)号：US08673710B2

    公开(公告)日：2014-03-18

    申请号：US13197387

    申请日：2011-08-03

    Applicant: Stephan Kronholz ,  Rohit Pal

    Inventor： Stephan Kronholz ,  Rohit Pal

    IPC: H01L21/8238

    CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L21/823814

    Abstract: When forming sophisticated high-k metal gate electrode structures, the uniformity of the device characteristics may be enhanced by growing a threshold adjusting semiconductor alloy on the basis of a hard mask regime, which may result in a less pronounced surface topography, in particular in densely packed device areas. To this end, in some illustrative embodiments, a deposited hard mask material may be used for selectively providing an oxide mask of reduced thickness and superior uniformity.

    Abstract translation: 当形成复杂的高k金属栅电极结构时，可以通过基于硬掩模方式生长阈值调节半导体合金来增强器件特性的均匀性，这可能导致不太显着的表面形貌，特别是在密集 包装设备区域。 为此，在一些说明性实施例中，沉积的硬掩模材料可用于选择性地提供厚度减小和均匀性优异的氧化物掩模。

    Methods for protecting film layers while removing hardmasks during fabrication of semiconductor devices
    27.
    发明授权
    Methods for protecting film layers while removing hardmasks during fabrication of semiconductor devices 有权
    在制造半导体器件期间去除硬掩模的同时保护膜层的方法

    公开(公告)号：US08278165B2

    公开(公告)日：2012-10-02

    申请号：US12577628

    申请日：2009-10-12

    Applicant: Rohit Pal ,  Janice Monzet

    Inventor： Rohit Pal ,  Janice Monzet

    IPC: H01L21/8238

    CPC classification number: H01L21/823807 ,  H01L21/31111 ,  H01L21/823878

    Abstract: Methods for fabricating semiconductor devices are provided. The methods include providing a semiconductor substrate having pFET and nFET regions, each having active areas and shallow trench isolation. A hardmask layer is formed overlying the semiconductor substrate. A photoresist layer is provided over the hardmask layer. The phoresist layer is patterned. An exposed portion of the hardmask layer is removed from one of the pFET region and nFET region with the patterned photoresist acting as an etch mask to define a masked region and an unmasked region. An epitaxial silicon layer is formed on the active area in the unmasked region. A protective oxide layer is formed overlying the epitaxial silicon layer. The hardmask layer is removed from the masked region with the protective oxide layer protecting the epitaxial silicon layer during such removal step. The protective oxide layer is removed from the epitaxial silicon layer.

    Abstract translation: 提供制造半导体器件的方法。 所述方法包括提供具有pFET和nFET区域的半导体衬底，每个具有有源区和浅沟槽隔离。 形成覆盖半导体衬底的硬掩模层。 在硬掩模层上提供光致抗蚀剂层。 光刻胶层被图案化。 硬掩模层的暴露部分从pFET区域和nFET区域中的一个去除，图案化的光致抗蚀剂用作蚀刻掩模以限定掩蔽区域和未掩模区域。 在未掩模区域的有源区域上形成外延硅层。 形成覆盖在外延硅层上的保护性氧化物层。 在这种去除步骤期间，保护氧化层保护外延硅层，从屏蔽区域去除硬掩模层。 从外延硅层去除保护氧化物层。

    Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods
    28.
    发明授权
    Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods 有权
    用于在由这种方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法

    公开(公告)号：US08084828B2

    公开(公告)日：2011-12-27

    申请号：US12815129

    申请日：2010-06-14

    Applicant: Rohit Pal ,  Man Fai Ng ,  David Brown

    Inventor： Rohit Pal ,  Man Fai Ng ,  David Brown

    IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC classification number: H01L29/6656 ,  H01L21/28114 ,  H01L21/28247

    Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. In an embodiment, a method for fabricating a semiconductor device comprises forming a gate stack comprising a first gate stack-forming layer overlying a semiconductor substrate and forming first sidewall spacers about sidewalls of the gate stack. After the step of forming the first sidewall spacers, a portion of the first gate stack-forming layer is exposed. The exposed portion is anisotropically etched using the gate stack and the first sidewall spacers as an etch mask. Second sidewall spacers are formed adjacent the first sidewall spacers after the step of anisotropically etching.

    Abstract translation: 提供了在由这些方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法。 在一个实施例中，一种用于制造半导体器件的方法包括：形成包括覆盖在半导体衬底上的第一栅极叠层形成层并且围绕栅堆叠的侧壁形成第一侧壁隔离物的栅叠层。 在形成第一侧壁间隔物的步骤之后，暴露第一栅叠层形成层的一部分。 使用栅极堆叠和第一侧壁间隔物作为蚀刻掩模来各向异性蚀刻暴露部分。 在各向异性蚀刻的步骤之后，第二侧壁间隔物邻近第一侧壁间隔件形成。

    SELF-ALIGNED EMBEDDED SiGe STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    29.
    发明申请
    SELF-ALIGNED EMBEDDED SiGe STRUCTURE AND METHOD OF MANUFACTURING THE SAME 失效
    自对准嵌入式SiGe结构及其制造方法

    公开(公告)号：US20110298008A1

    公开(公告)日：2011-12-08

    申请号：US12795683

    申请日：2010-06-08

    Applicant: Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

    Inventor： Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/66636 ,  H01L21/3247 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7848

    Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

    Abstract translation: 低能量表面通过栅极堆叠的每一侧的沟槽表面的高温退火形成。 半导体层的材料在高温退火期间回流，使得低能表面是与半导体层的表面法线成非正交角的结晶表面。 在半导体层上选择性地生长晶格失配的半导体材料以填充沟槽，从而在晶体管的源极和漏极区域中形成嵌入的晶格失配的半导体材料部分。 嵌入的晶格不匹配的半导体材料部分可以原位掺杂而不增加穿通。 或者，可以采用固有选择性外延和离子注入的组合来形成深的源极和漏极区域。

    Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods
    30.
    发明授权
    Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods 有权
    用于在由这种方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法

    公开(公告)号：US07763508B2

    公开(公告)日：2010-07-27

    申请号：US12330292

    申请日：2008-12-08

    Applicant: Rohit Pal ,  Man Fai Ng ,  David Brown

    Inventor： Rohit Pal ,  Man Fai Ng ,  David Brown

    IPC: H01L21/336 ,  H01L21/8234

    CPC classification number: H01L29/6656 ,  H01L21/28114 ,  H01L21/28247

    Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. In an embodiment, a method for fabricating a semiconductor device comprises forming a gate stack comprising a first gate stack-forming layer overlying a semiconductor substrate and forming first sidewall spacers about sidewalls of the gate stack. After the step of forming the first sidewall spacers, a portion of the first gate stack-forming layer is exposed. The exposed portion is anisotropically etched using the gate stack and the first sidewall spacers as an etch mask. Second sidewall spacers are formed adjacent the first sidewall spacers after the step of anisotropically etching.

    Abstract translation: 提供了在由这些方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法。 在一个实施例中，一种用于制造半导体器件的方法包括：形成包括覆盖在半导体衬底上的第一栅极叠层形成层并且围绕栅堆叠的侧壁形成第一侧壁隔离物的栅叠层。 在形成第一侧壁间隔物的步骤之后，暴露第一栅叠层形成层的一部分。 使用栅极堆叠和第一侧壁间隔物作为蚀刻掩模来各向异性蚀刻暴露部分。 在各向异性蚀刻的步骤之后，第二侧壁间隔物邻近第一侧壁间隔件形成。

Patent Agency Ranking