公开(公告)号：US20220189993A1

公开(公告)日：2022-06-16

申请号：US17122360

申请日：2020-12-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Roshan TIRUKKONDA ,  Ramy Nashed Bassely SAID ,  Senaka KANAKAMEDALA ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR ,  Fei ZHOU

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers and memory stack structures vertically extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of ferroelectric memory elements surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers. Each of the ferroelectric memory elements includes a respective vertical stack of a first ferroelectric material portion and a second ferroelectric material portion that differs from the first ferroelectric material portion by at least one of a material composition and a lateral thickness.

公开(公告)号：US20210193585A1

公开(公告)日：2021-06-24

申请号：US16722824

申请日：2019-12-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Senaka KANAKAMEDALA ,  Fei ZHOU ,  Raghuveer S. MAKALA ,  Yao-Sheng LEE

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556

Abstract: A structure, such as a semiconductor device, includes metal line structures located over a substrate and laterally spaced apart from each other. Each of the metal line structures includes planar metallic liner including a first metal element and a metal line body portion includes a second metal element that is different from the first metal element. Metal-organic framework (MOF) material portions are located between neighboring pairs of the metal line structures and contain metal ions or clusters of the first metal element and organic ligands connected to the metal ions or clusters of the first metal element. Air gaps may be formed in the MOF material portions to further reduce the effective dielectric constant.

公开(公告)号：US20210050372A1

公开(公告)日：2021-02-18

申请号：US16743436

申请日：2020-01-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Yanli ZHANG ,  Seung-Yeul YANG ,  Fei ZHOU

IPC: H01L27/11597 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A ferroelectric memory device includes a semiconductor channel, a gate electrode, and a ferroelectric memory element located between the semiconductor channel and the gate electrode. The ferroelectric memory element includes at least one ferroelectric material portion and at least one antiferroelectric material portion.

公开(公告)号：US20210050371A1

公开(公告)日：2021-02-18

申请号：US16541289

申请日：2019-08-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Seung-Yeul YANG ,  Fei ZHOU ,  Adarsh RAJASHEKHAR

IPC: H01L27/11597 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11592

Abstract: A three-dimensional ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where each of the electrically conductive layers contains a respective transition metal nitride liner and a respective conductive fill material layer, a vertical semiconductor channel vertically extending through the alternating stack, a vertical stack of transition metal nitride spacers laterally surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers, and discrete ferroelectric material portions laterally surrounding the respective transition metal nitride spacers and located at the levels of the electrically conductive layers.

公开(公告)号：US20190287916A1

公开(公告)日：2019-09-19

申请号：US16020008

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Adarsh RAJASHEKHAR ,  Tatsuya HINOUE ,  Tomoyuki OBU ,  Tomohiro UNO ,  Yusuke MUKAE

IPC: H01L23/532 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768 ,  H01L29/49

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each of the electrically conductive layers includes a stack of a compositionally graded diffusion barrier and a metal fill material portion, and the compositionally graded diffusion barrier includes a substantially amorphous region contacting the interface between the compositionally graded diffusion barrier and a substantially crystalline region that is spaced from the interface by the amorphous region. The substantially crystalline region effectively blocks atomic diffusion, and the amorphous region induces formation of large grains during deposition of the metal fill material portions.

公开(公告)号：US20170373079A1

公开(公告)日：2017-12-28

申请号：US15483862

申请日：2017-04-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Fumitaka AMANO ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Keerti SHUKLA

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L21/768 ,  H01L23/532 ,  H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11556 ,  H01L21/28282 ,  H01L21/76847 ,  H01L23/53266 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

Abstract: Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. A barrier layer stack including a crystalline electrically conductive barrier layer and an amorphous barrier layer is formed in the backside recesses prior to formation of a metal fill material layer.

公开(公告)号：US20250040139A1

公开(公告)日：2025-01-30

申请号：US18794727

申请日：2024-08-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei ZHOU ,  Kartik SONDHI ,  Senaka KANAKAMEDALA ,  Wei CAO

IPC: H10B43/27 ,  G11C16/04 ,  H10B43/10 ,  H10B43/35

Abstract: A memory device includes a semiconductor source line layer containing silicon and electrical dopants, an alternating stack of insulating layers and electrically conductive layers located over the semiconductor source line layer, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening. The memory opening fill structure includes a memory film, a vertical semiconductor channel including silicon that is laterally surrounded by the memory film, and a silicon-germanium structure contacting an end portion of the vertical semiconductor channel and contacting the semiconductor source line.

公开(公告)号：US20240121960A1

公开(公告)日：2024-04-11

申请号：US18348702

申请日：2023-07-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Rahul SHARANGPANI ,  Kartik SONDHI

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack and having a lateral undulation in a vertical cross-sectional profile such that the memory opening laterally protrudes outward at levels of the electrically conductive layers, and a memory opening fill structure located in the memory opening and including a vertical stack of blocking dielectric material portions located at the levels of the electrically conductive layers, a vertical stack of discrete memory elements located at the levels of the electrically conductive layers and including a respective contoured charge storage material portion, a tunneling dielectric layer overlying the contoured inner sidewalls of the tubular charge storage material portion, and a vertical semiconductor channel.

公开(公告)号：US20240064991A1

公开(公告)日：2024-02-22

申请号：US17820997

申请日：2022-08-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kartik SONDHI ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Tiffany SANTOS ,  Fei ZHOU ,  Joyeeta NAG ,  Bhagwati PRASAD ,  Adarsh RAJASHEKHAR

IPC: H01L27/11597 ,  H01L27/1159

CPC classification number: H01L27/11597 ,  H01L27/1159

Abstract: A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

公开(公告)号：US20230354608A1

公开(公告)日：2023-11-02

申请号：US18344411

申请日：2023-06-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Noriyuki NAGAHATA ,  Masanori TSUTSUMI ,  Fei ZHOU ,  Raghuveer S. MAKALA

IPC: H10B43/27 ,  G11C16/04 ,  H10B43/10 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H01L21/768

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H10B43/10 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H01L21/76843

Abstract: A method of forming a memory device includes forming an alternating stack of disposable material layers and silicon nitride layers over a substrate, forming a memory opening through the alternating stack, forming a memory film in the memory opening, forming a vertical semiconductor channel over the memory film in the memory opening, forming a backside trench through the alternating stack, forming laterally-extending cavities by removing the disposable material layers selective to the silicon nitride layers through the backside trench, oxidizing portions of the silicon nitride layers exposed in the laterally-extending cavities to form insulating layers, and replacing remaining portions of the silicon nitride layers with electrically conductive layers.