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    PULSE CONVERTER CIRCUIT
    24.
    发明申请
    PULSE CONVERTER CIRCUIT 审中-公开
    脉冲转换器电路

    公开(公告)号：US20160065191A1

    公开(公告)日：2016-03-03

    申请号：US14936292

    申请日：2015-11-09

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Toshihiko SAITO

    IPC: H03K5/04 ,  H01L27/092

    CPC classification number: H03K5/04 ,  H01L27/092 ,  H01L27/1233 ,  H01L27/1237 ,  H01L27/1251 ,  H01L29/7869

    Abstract: A pulse converter circuit includes a logic circuit to which a first signal is input and from which a second signal is output. The logic circuit includes a p-channel transistor which determines whether a voltage of the second signal is set to a first voltage depending on a voltage of the gate; and an n-channel transistor which determines whether the voltage of the second signal is set to a second voltage, which is higher than the first voltage, depending on a voltage of the gate. The p-channel transistor includes a semiconductor layer containing an element of a group 14. The n-channel transistor includes an oxide semiconductor layer.

    Abstract translation: 脉冲转换器电路包括输入第一信号并输出​​第二信号的逻辑电路。 逻辑电路包括一个p沟道晶体管，它确定第二个信号的电压是否根据栅极的电压被设置为第一个电压; 以及n沟道晶体管，其根据栅极的电压确定第二信号的电压是否被设定为高于第一电压的第二电压。 p沟道晶体管包括含有组14的元件的半导体层.n沟道晶体管包括氧化物半导体层。

    SEMICONDUCTOR MEMORY DEVICE
    25.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20150097183A1

    公开(公告)日：2015-04-09

    申请号：US14571392

    申请日：2014-12-16

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Toshihiko SAITO

    IPC: H01L27/108 ,  H01L29/786 ,  H01L49/02 ,  H01L27/06

    CPC classification number: H01L29/7869 ,  G11C11/404 ,  G11C11/565 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/1082 ,  H01L28/86

    Abstract: A semiconductor memory device includes a bit line; two or more word lines; and a memory cell including two or more sub memory cells that each include a transistor and a capacitor. One of a source and a drain of the transistor is connected to the bit line, the other of the source and the drain of the transistor is connected to the capacitor, a gate of the transistor is connected to one of the word lines, and each of the sub memory cells has a different capacitance of the capacitor.

    Abstract translation: 半导体存储器件包括位线; 两条或多条字线; 以及包括两个或更多个子存储器单元的存储单元，每个子存储器单元包括晶体管和电容器。 晶体管的源极和漏极之一连接到位线，晶体管的源极和漏极中的另一个连接到电容器，晶体管的栅极连接到字线之一，并且每个 的子存储单元具有不同于电容器的电容。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    26.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20150037932A1

    公开(公告)日：2015-02-05

    申请号：US14459597

    申请日：2014-08-14

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Toshihiko SAITO ,  Takehisa HATANO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Junichi KOEZUKA ,  Yuichi SATO ,  Shinji OHNO

    IPC: H01L29/66 ,  H01L21/02

    CPC classification number: H01L29/66969 ,  H01L21/02488 ,  H01L21/02565 ,  H01L27/1225 ,  H01L29/786 ,  H01L29/78606 ,  H01L29/7869

    Abstract: A semiconductor device which includes an oxide semiconductor and has favorable electrical characteristics is provided. In the semiconductor device, an oxide semiconductor film and an insulating film are formed over a substrate. Side surfaces of the oxide semiconductor film are in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. A gate insulating film is formed on and in contact with the oxide semiconductor film. A gate electrode with sidewall insulating films is formed over the gate insulating film. A source electrode and a drain electrode are formed in contact with the oxide semiconductor film and the insulating film.

    Abstract translation: 提供了包括氧化物半导体并且具有良好的电特性的半导体器件。 在半导体器件中，在衬底上形成氧化物半导体膜和绝缘膜。 氧化物半导体膜的侧面与绝缘膜接触。 氧化物半导体膜包括沟道形成区域和包含掺杂剂的区域，沟道形成区域夹在其间。 栅极绝缘膜与氧化物半导体膜形成并接触。 在栅绝缘膜上形成具有侧壁绝缘膜的栅电极。 源电极和漏电极形成为与氧化物半导体膜和绝缘膜接触。

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
    27.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 审中-公开
    制造半导体器件和半导体器件的方法

    公开(公告)号：US20140349444A1

    公开(公告)日：2014-11-27

    申请号：US14454071

    申请日：2014-08-07

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Toshihiko SAITO ,  Atsuo ISOBE ,  Kazuya HANAOKA ,  Sho NAGAMATSU

    IPC: H01L29/66 ,  H01L21/465 ,  H01L21/463 ,  H01L21/02 ,  H01L21/44

    CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L21/44 ,  H01L21/463 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/14632 ,  H01L27/14687 ,  H01L29/04 ,  H01L29/78 ,  H01L29/7869

    Abstract: A minute transistor and the method of manufacturing the minute transistor. A source electrode layer and a drain electrode layer are each formed in a corresponding opening formed in an insulating layer covering a semiconductor layer. The opening of the source electrode layer and the opening of the drain electrode layer are formed separately in two distinct steps. The source electrode layer and the drain electrode layer are formed by depositing a conductive layer over the insulating layer and in the openings, and subsequently removing the part located over the insulating layer by polishing. This manufacturing method allows for the source electrode later and the drain electrode layer to be formed close to each other and close to a channel forming region of the semiconductor layer. Such a structure leads to a transistor having high electrical characteristics and a high manufacturing yield even in the case of a minute structure.

    Abstract translation: 一分钟晶体管和微晶体管的制造方法。 源极电极层和漏极电极层各自形成在形成在覆盖半导体层的绝缘层中的对应的开口中。 源电极层的开口和漏电极层的开口分开形成两个不同的步骤。 源极电极层和漏电极层通过在绝缘层上和开口中沉积导电层而形成，然后通过抛光去除位于绝缘层之上的部分。 该制造方法允许稍后的源极电极和漏极电极层彼此靠近并且靠近半导体层的沟道形成区域。 这种结构导致即使在微小结构的情况下也具有高电特性和高制造成品率的晶体管。

    MEMORY DEVICE
    28.
    发明申请
    MEMORY DEVICE 审中-公开
    内存设备

    公开(公告)号：US20140209987A1

    公开(公告)日：2014-07-31

    申请号：US14227408

    申请日：2014-03-27

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Kiyoshi KATO ,  Toshihiko SAITO

    IPC: H01L27/108

    CPC classification number: H01L27/10808 ,  H01L21/84 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/1203 ,  H01L28/91

    Abstract: It is an object to provide a memory device where an area occupied by a memory cell is small, and moreover, a memory device where an area occupied by a memory cell is small and a data holding period is long. A memory device includes a bit line, a capacitor, a first insulating layer provided over the bit line and including a groove portion, a semiconductor layer, a second insulating layer in contact with the semiconductor layer, and a word line in contact with the second insulating layer. Part of the semiconductor layer is electrically connected to the bit line in a bottom portion of the groove portion, and another part of the semiconductor layer is electrically connected to one electrode of the capacitor in a top surface of the first insulating layer.

    Abstract translation: 本发明的目的是提供一种存储器单元所占据的区域小的存储器件，而且存储器单元所占据的区域小且数据保持期间长的存储器件。 存储器件包括位线，电容器，设置在位线上并包括沟槽部分的第一绝缘层，半导体层，与半导体层接触的第二绝缘层，以及与第二绝缘层接触的字线 绝缘层。 半导体层的一部分电连接到槽部的底部的位线，半导体层的另一部分与第一绝缘层的上表面的电容器的一个电极电连接。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    29.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20140127868A1

    公开(公告)日：2014-05-08

    申请号：US14151036

    申请日：2014-01-09

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Toshihiko SAITO ,  Atsuo ISOBE ,  Kazuya HANAOKA ,  Junichi KOEZUKA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Akihiro ISHIZUKA

    IPC: H01L29/66

    CPC classification number: H01L29/66477 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

    Abstract: A miniaturized transistor is provided with high yield. Further, a semiconductor device which has high on-state characteristics and which is capable of high-speed response and high-speed operation is provided. In the semiconductor device, an oxide semiconductor layer, a gate insulating layer, a gate electrode layer, an insulating layer, a conductive film, and an interlayer insulating layer are stacked in this order. A source electrode layer and a drain electrode layer are formed in a self-aligned manner by cutting the conductive film so that the conductive film over the gate electrode layer and the conductive layer is removed and the conductive film is divided. An electrode layer which is in contact with the oxide semiconductor layer and overlaps with a region in contact with the source electrode layer and the drain electrode layer is provided.

    Abstract translation: 提供了一种小型化的晶体管，其产率高。 此外，提供了具有高导通状态特性并且能够进行高速响应和高速操作的半导体器件。 在半导体装置中，依次层叠氧化物半导体层，栅极绝缘层，栅极电极层，绝缘层，导电膜和层间绝缘层。 通过切割导电膜以自对准的方式形成源电极层和漏电极层，从而去除栅极电极层和导电层上的导电膜，并且导电膜被分割。 设置与氧化物半导体层接触并与与源极电极层和漏极电极层接触的区域重叠的电极层。

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