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    Method for programming a non-volatile memory cell comprising a shared select transistor gate
    21.
    发明授权
    Method for programming a non-volatile memory cell comprising a shared select transistor gate 有权
    用于对包括共享选择晶体管栅极的非易失性存储单元进行编程的方法

    公开(公告)号：US09443598B2

    公开(公告)日：2016-09-13

    申请号：US14719913

    申请日：2015-05-22

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

    IPC: G11C16/04 ,  G11C16/14 ,  H01L27/115

    CPC classification number: G11C16/14 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/0458 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11517

    Abstract: The present disclosure relates to a method for controlling two twin memory cells each comprising a floating-gate transistor comprising a state control gate, in series with a select transistor comprising a select control gate common to the two memory cells, the drains of the floating-gate transistors being connected to a same bit line, the method comprising steps of programming the first memory cell by hot-electron injection, by applying a positive voltage to the bit line and a positive voltage to the state control gate of the first memory cell, and simultaneously, of applying to the state control gate of the second memory cell a positive voltage capable of causing a programming current to pass through the second memory cell, without switching it to a programmed state.

    Abstract translation: 本公开涉及一种用于控制两个双存储单元的方法，每个双存储器单元包括浮置晶体管，其包括状态控制栅极，与包括两个存储单元共用的选择控制栅极的选择晶体管串联， 栅极晶体管连接到相同的位线，该方法包括以下步骤：通过对位线施加正电压并将正电压施加到第一存储单元的状态控制栅极，通过热电子注入来对第一存储单元进行编程， 并且同时向第二存储单元的状态控制栅极施加能够使编程电流通过第二存储单元的正电压，而不将其切换到编程状态。

    Hot-carrier injection programmable memory and method of programming such a memory
    22.
    发明授权
    Hot-carrier injection programmable memory and method of programming such a memory 有权
    热载体注入可编程存储器和编程这种存储器的方法

    公开(公告)号：US09224482B2

    公开(公告)日：2015-12-29

    申请号：US14528780

    申请日：2014-10-30

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier ,  Julien Delalleau

    IPC: G11C16/00 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  H01L29/788 ,  H01L27/115 ,  H01L29/423

    CPC classification number: G11C16/10 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34 ,  G11C16/3418 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7881

    Abstract: The present disclosure relates to a memory comprising at least one word line comprising a row of split gate memory cells each comprising a selection transistor section comprising a selection gate and a floating-gate transistor section comprising a floating gate and a control gate. According to the present disclosure, the memory comprises a source plane common to the memory cells of the word line, to collect programming currents passing through memory cells during their programming, and the selection transistor sections of the memory cells are connected to the source plane. A programming current control circuit is configured to control the programming current passing through the memory cells by acting on a selection voltage applied to a selection line.

    Abstract translation: 本公开涉及包括至少一个字线的存储器，该字线包括一行分离栅极存储单元，每行分离栅极存储单元包括选择晶体管部分，该选择晶体管部分包括选择栅极和包括浮置栅极和控制栅极的浮动栅极晶体管部分。 根据本公开，存储器包括与字线的存储器单元共同的源平面，以在编程期间收集通过存储器单元的编程电流，并且存储器单元的选择晶体管部分连接到源极平面。 编程电流控制电路被配置为通过作用于施加到选择线的选择电压来控制通过存储器单元的编程电流。

    COMPACT NON-VOLATILE MEMORY DEVICE OF THE TYPE WITH CHARGE TRAPPING IN A DIELECTRIC INTERFACE
    26.
    发明申请
    COMPACT NON-VOLATILE MEMORY DEVICE OF THE TYPE WITH CHARGE TRAPPING IN A DIELECTRIC INTERFACE 审中-公开

    公开(公告)号：US20190371805A1

    公开(公告)日：2019-12-05

    申请号：US16542511

    申请日：2019-08-16

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

    IPC: H01L27/11563 ,  H01L27/11536

    Abstract: A memory device includes a first state transistor and a second state transistor having a common control gate. A first selection transistor is buried in the semiconductor body and coupled to the first state transistor so that current paths of the first selection transistor and first state transistor are coupled in series. A second selection transistor is buried in the semiconductor body and coupled to the second state transistor so that current paths of the second selection transistor and second state transistor are coupled in series. The first and second selection transistors have a common buried selection gate. A dielectric region is located between the common control gate and the semiconductor body. A first bit line is coupled to the first state transistor and a second bit line is coupled to the second state transistor.

    MEMORY CELL HAVING A VERTICAL SELECTION GATE FORMED IN AN FDSOI SUBSTRATE
    30.
    发明申请
    MEMORY CELL HAVING A VERTICAL SELECTION GATE FORMED IN AN FDSOI SUBSTRATE 审中-公开
    在FDSOI基板中形成垂直选择栅的存储单元

    公开(公告)号：US20160372561A1

    公开(公告)日：2016-12-22

    申请号：US15252090

    申请日：2016-08-30

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Arnaud Regnier ,  Jean-Michel Mirabel ,  Stephan Niel ,  Francesco La Rosa

    IPC: H01L29/423 ,  H01L27/115 ,  H01L29/788 ,  H01L29/66

    CPC classification number: H01L29/42336 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7831 ,  H01L29/7881 ,  H01L29/7885 ,  H01L29/7889

    Abstract: A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.

    Abstract translation: 形成在半导体衬底中的存储单元包括在衬底中形成的沟槽中垂直延伸的选择栅极，并且通过栅极氧化物的第一层与衬底隔离，水平浮动栅极延伸在衬底上方并与衬底隔离，并与衬底隔离 栅极氧化物的第二层和在浮置栅极上方延伸的水平控制栅极。 选择栅极覆盖浮动栅极的侧面。 浮置栅极仅由第一层栅极氧化物与选择栅极分离，并且与垂直沟道区分离，仅沿着选择栅极在衬底中延伸，仅由栅极氧化物的第二层分离。

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