公开(公告)号：US20230240068A1

公开(公告)日：2023-07-27

申请号：US18194258

申请日：2023-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung Yang ,  Byungjin Lee ,  Bumkyu Kang ,  Dong-Sik Lee

IPC: H10B41/46 ,  H01L23/528 ,  H01L23/522 ,  G11C16/08 ,  G11C7/18 ,  H10B41/10 ,  H10B41/20 ,  H10B41/48 ,  H10B43/10 ,  H10B43/20 ,  H10B43/40

CPC classification number: H10B41/46 ,  G11C7/18 ,  G11C16/08 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/20 ,  H10B41/48 ,  H10B43/10 ,  H10B43/20 ,  H10B43/40

Abstract: A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.

公开(公告)号：US10903236B2

公开(公告)日：2021-01-26

申请号：US16663228

申请日：2019-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kangyoon Choi ,  Dong-Sik Lee ,  Jongwon Kim ,  Gilsung Lee ,  Eunsuk Cho ,  Byungyong Choi ,  Sung-Min Hwang

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/04 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/28 ,  H01L21/02

Abstract: A three-dimensional (3D) semiconductor memory device includes a substrate that includes a cell array region and a connection region, a dummy trench formed on the connection region, an electrode structure on the substrate and that includes vertically stacked electrodes that have a staircase structure on the connection region, a dummy insulating structure disposed in the dummy trench, the dummy insulating structure including an etch stop pattern spaced apart from the substrate and the electrode structure, a cell channel structure disposed on the cell array region and that penetrates the electrode structure and makes contact with the substrate, and a dummy channel structure disposed on the connection region and that penetrates the electrode structure and a portion of the dummy insulating structure and that makes contact with the etch stop pattern.

公开(公告)号：US09659958B2

公开(公告)日：2017-05-23

申请号：US15291521

申请日：2016-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Hoon Lee ,  Keejeong Rho ,  Sejun Park ,  Jinhyun Shin ,  Dong-Sik Lee ,  Woong-Seop Lee

IPC: H01L27/115 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  G11C16/08 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/1157

Abstract: A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.

公开(公告)号：US09601577B1

公开(公告)日：2017-03-21

申请号：US15251510

申请日：2016-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Sik Lee ,  Youngwoo Kim ,  Jinhyun Shin ,  Jung Hoon Lee

IPC: H01L29/10 ,  H01L27/115 ,  H01L23/522 ,  H01L23/528 ,  H01L29/423 ,  G11C16/08

CPC classification number: H01L27/11551 ,  H01L21/26506 ,  H01L21/28158 ,  H01L21/823462 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/11246 ,  H01L27/115 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11597 ,  H01L28/00 ,  H01L29/1083 ,  H01L29/42368

Abstract: A vertically integrated circuit device can include a substrate having a first region reserved for first functional circuits of the vertically integrated circuit device, where the first functional circuits has a substantially constant top surface level across the first region and having a second region reserved for second functional circuits of the vertically integrated circuit device and spaced apart from the first region. The second functional circuits can have a varied top surface level across the second region. A doped oxidation suppressing material can be included in the substrate and can extend from the first region to the second region at an interface of the substrate with the first functional circuits and the second functional circuits, respectively.

公开(公告)号：US08878332B2

公开(公告)日：2014-11-04

申请号：US14248517

申请日：2014-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Hoon Na ,  Young-Woo Park ,  Dong-Hwa Kwak ,  Tae-Yong Kim ,  Jee-Hoon Han ,  Jang-Hyun You ,  Dong-Sik Lee ,  Su-Jin Park

IPC: H01L21/70 ,  H01L21/76 ,  H01L27/02 ,  H01L27/11

CPC classification number: H01L27/0207 ,  H01L21/28273 ,  H01L27/11 ,  H01L27/11519 ,  H01L27/11524

Abstract: A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.

Abstract translation: 一种制造非易失性存储器件的方法包括提供具有由多个沟槽限定的有源区的衬底，在具有多个沟槽的衬底上形成第一隔离层，在第一隔离层上形成牺牲层以填充沟槽， 所述牺牲层包括填充所述沟槽的下部的第一区域和除所述下部以外的第二区域填充部分，去除所述牺牲层的所述第二区域，在所述第一隔离层上形成第二隔离层和在所述第一隔离层的所述第一区域 牺牲层，通过去除牺牲层的第一区域在沟槽中形成气隙，以及在保持气隙的同时去除第一隔离层的一部分和第二隔离层的一部分。

公开(公告)号：US20140248755A1

公开(公告)日：2014-09-04

申请号：US14279786

申请日：2014-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Sik Lee ,  Jang-Hyun You ,  Jee-Hoon Han ,  Young-Woo Park ,  Sung-Hoi Hur ,  Sang-Ick Joo

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/76229 ,  H01L21/764

Abstract: A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.

Abstract translation: 制造非易失性存储器件的方法包括在衬底中形成限定器件隔离区域的衬底中的沟槽，并且其间的有源区域。 沟槽和其间的有源区延伸到衬底的第一和第二器件区域。 牺牲层形成在第一器件区域中的有源区之间的沟槽中，并且形成绝缘层以基本上填充第二器件区域中的有源区之间的沟槽。 选择性地去除第一器件区域中的沟槽中的牺牲层的至少一部分以限定沿着第一器件区域中的有源区之间的沟槽延伸的间隙区域，同时基本上将绝缘层保持在有源区域之间的沟槽中 在第二设备区域中。 还讨论了相关的方法和设备。