公开(公告)号：US10211339B2

公开(公告)日：2019-02-19

申请号：US15397011

申请日：2017-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： YeonCheol Heo ,  Mirco Cantoro

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423

Abstract: A semiconductor device includes a semiconductor substrate including a first source/drain region formed in an upper portion of the semiconductor substrate, a metal silicide layer that covers a top surface of the first source/drain region, and a semiconductor pillar that penetrates the metal silicide layer and is connected to the semiconductor substrate. The semiconductor pillar includes a second source/drain region formed in an upper portion of the semiconductor pillar, a gate electrode on the metal silicide layer, with the gate electrode surrounding the semiconductor pillar in a plan view. A contact is connected to the metal silicide layer.

公开(公告)号：US20180294353A1

公开(公告)日：2018-10-11

申请号：US16003959

申请日：2018-06-08

Applicant: Samsung Electronics Co., Ltd

Inventor： Mirco Cantoro ,  Yeon-cheol Heo ,  Maria Toledano Luque

IPC: H01L29/78 ,  H01L29/207 ,  H01L29/66 ,  H01L29/423 ,  H01L21/306 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/04

CPC classification number: H01L29/7827 ,  H01L21/30612 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/20 ,  H01L29/207 ,  H01L29/42376 ,  H01L29/66522 ,  H01L29/66666

Abstract: An integrated circuit device may include a substrate including a main surface, a compound semiconductor nanowire extending from the main surface in a first direction perpendicular to the main surface and including a first section and a second section alternately arranged in the first direction, a gate electrode covering the first section, and a gate dielectric layer between the first section and the gate electrode. The first section and the second section may have the same composition as each other and may have different crystal phases from each other

公开(公告)号：US10020396B2

公开(公告)日：2018-07-10

申请号：US15350686

申请日：2016-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  Yeon-cheol Heo ,  Maria Toledano Luque

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/306 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/207 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L21/30612 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/20 ,  H01L29/207 ,  H01L29/42376 ,  H01L29/66522 ,  H01L29/66666

Abstract: An integrated circuit device may include a substrate including a main surface, a compound semiconductor nanowire extending from the main surface in a first direction perpendicular to the main surface and including a first section and a second section alternately arranged in the first direction, a gate electrode covering the first section, and a gate dielectric layer between the first section and the gate electrode. The first section and the second section may have the same composition as each other and may have different crystal phases from each other.

公开(公告)号：US20170317084A1

公开(公告)日：2017-11-02

申请号：US15480669

申请日：2017-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  Tae-yong Kwon ,  Jae-young Park ,  Dong-hoon Hwang ,  Han-ki Lee ,  So-ra You

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/762 ,  H01L21/768 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7854

Abstract: An integrated circuit device as provided herein may include a device region and an inter-device isolation region. Within the device region, a fin-type active region may protrude from a substrate, and opposite sidewalls of the fin-type active region may be covered by an inner isolation layer. An outer isolation layer may fill an outer deep trench in the inter-device isolation region. The inner isolation layer may extend away from the device region at an inner sidewall of the outer deep trench and into the inter-device isolation region. There may be multiple fin-type active regions, and trenches therebetween. The outer deep trench and the trenches between the plurality of fin-type active regions may be of different heights. The integrated circuit device and methods of manufacturing described herein may reduce a possibility that various defects or failures may occur due to an unnecessary fin-type active region remaining around the device region.

公开(公告)号：US20170271508A1

公开(公告)日：2017-09-21

申请号：US15397011

申请日：2017-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： YeonCheol Heo ,  Mirco Cantoro

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7827 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/66666

Abstract: A semiconductor device includes a semiconductor substrate including a first source/drain region formed in an upper portion of the semiconductor substrate, a metal silicide layer that covers a top surface of the first source/drain region, and a semiconductor pillar that penetrates the metal silicide layer and is connected to the semiconductor substrate. The semiconductor pillar includes a second source/drain region formed in an upper portion of the semiconductor pillar, a gate electrode on the metal silicide layer, with the gate electrode surrounding the semiconductor pillar in a plan view. A contact is connected to the metal silicide layer.

公开(公告)号：US12132046B2

公开(公告)日：2024-10-29

申请号：US17466043

申请日：2021-09-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jun Kim ,  Beomjin Park ,  Dong Il Bae ,  Mirco Cantoro

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L27/088 ,  H01L29/41775 ,  H01L29/42372

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The semiconductor device includes a plurality of gate structures that are spaced apart from each other in a first direction on a substrate and extend in a second direction intersecting the first direction, and a plurality of separation patterns penetrating immediately neighboring ones of the plurality of gate structures, respectively. Each of the plurality of separation patterns separates a corresponding one of the neighboring gate structures into a pair of gate structures that are spaced apart from each other in the second direction. The plurality of separation patterns are spaced apart from and aligned with each other along the first direction.

公开(公告)号：US11843051B2

公开(公告)日：2023-12-12

申请号：US17860820

申请日：2022-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mirco Cantoro ,  Yeoncheol Heo

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/10 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/8258

CPC classification number: H01L29/7849 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/785 ,  H01L21/8258 ,  H01L21/823481

Abstract: The present disclosure relates to a field-effect transistor and a method of fabricating the same. A field-effect transistor includes a semiconductor substrate including a first semiconductor material having a first lattice constant, and a fin structure on the semiconductor substrate. The fin structure includes a second semiconductor material having a second lattice constant that is different from the first lattice constant. The fin structure further includes a lower portion that is elongated in a first direction, a plurality of upper portions protruding from the lower portion and elongated in a second direction that is different from the first direction, and a gate structure crossing the plurality of upper portions.

公开(公告)号：US11342456B2

公开(公告)日：2022-05-24

申请号：US17144444

申请日：2021-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woobin Song ,  Heiseung Kim ,  Mirco Cantoro ,  Sangwoo Lee ,  Minhee Cho ,  Beomyong Hwang

IPC: H01L29/78 ,  H01L29/161 ,  H01L21/02 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28

Abstract: A ferroelectric semiconductor device includes an active region extending in one direction, a gate insulating layer crossing the active region, a ferroelectric layer disposed on the gate insulating layer and including a hafnium oxide, a gate electrode layer disposed on the ferroelectric layer, and source/drain regions disposed on the active region to be adjacent to both sides of the gate insulating layer, wherein the ferroelectric layer includes 20% or more of orthorhombic crystals, and an upper surface of the source/drain region is located at a level equal to or higher than an upper surface of the ferroelectric layer.

公开(公告)号：US10714397B2

公开(公告)日：2020-07-14

申请号：US16541416

申请日：2019-08-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mirco Cantoro ,  Maria Toledano Luque ,  Yeoncheol Heo ,  Dong Il Bae

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/161 ,  H01L29/417 ,  H01L27/11 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material, patterning the semiconductor layer to form a preliminary active pattern, oxidizing at least two sidewalls of the preliminary active pattern to form an oxide layer on each of the at least two sidewalls of the preliminary active pattern, at least two upper patterns and a semiconductor pattern being formed in the preliminary active pattern when the oxide layers are formed, the semiconductor pattern being disposed between the at least two upper patterns, and removing the semiconductor pattern to form an active pattern, the active pattern including the at least two upper patterns. A concentration of the second semiconductor material in each of the at least two upper patterns is higher than a concentration of the second semiconductor material in the semiconductor pattern.

公开(公告)号：US10276564B2

公开(公告)日：2019-04-30

申请号：US15489093

申请日：2017-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  Yeon Cheol Heo ,  Byoung Gi Kim ,  Chang Min Yoe ,  Seung Chan Yun ,  Dong Hun Lee ,  Yun Il Lee ,  Hyung Suk Lee

IPC: H01L27/088 ,  H01L29/786 ,  H01L29/06 ,  H01L23/50 ,  H01L21/8234 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes a substrate having a first region and a second region; a first nanowire in the first region in a direction perpendicular to an upper surface of the substrate; a second nanowire in the second region in a direction perpendicular to the upper surface of the substrate and having a height less than that of the first nanowire; first source/drain regions at top portion and bottom portion of the first nanowire; second source/drain regions at top portion and bottom portion of the second nanowire; a first gate electrode surrounding the first nanowire between the first source/drain regions; and a second gate electrode surrounding the second nanowire between the second source/drain regions.