公开(公告)号：US10685979B1

公开(公告)日：2020-06-16

申请号：US16267625

申请日：2019-02-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ching-Huang Lu ,  Wei Zhao ,  Yanli Zhang ,  James Kai

IPC: H01L29/792 ,  H01L21/4763 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/06 ,  H01L21/768 ,  H01L21/311 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526

Abstract: Electrical isolation between adjacent stripes of drain-select-level electrically conductive layers can be provided by forming a drain-select-level isolation structure between neighboring rows of memory stack structures. The drain-select-level isolation structure can partially cut through upper regions of the neighboring rows of memory stack structures. Vertical semiconductor channels of the neighboring rows of memory stack structures include a lower tubular segment and an upper semi-tubular segment that contact the drain-select-level isolation structure. Electrical current through drain select levels is limited to the semi-tubular segment of each vertical semiconductor channel. Alternatively, the drain-select-level isolation structure can be formed around the memory stack structures within the neighboring rows of memory stack structures. Ion implantation can be used to suppress conduction of electrical current through portions of vertical semiconductor channels that are proximal to the drain-select-level isolation structure.

公开(公告)号：US20190280002A1

公开(公告)日：2019-09-12

申请号：US16020739

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Zhixin Cui ,  Murshed Chowdhury ,  Johann Alsmeier ,  Tong Zhang

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

Abstract: A first-tier structure including a first alternating stack of first insulating layers and first spacer material layers is formed over a substrate. First-tier memory openings and at least one type of first-tier contact openings can be formed simultaneously employing a same anisotropic etch process. The first-tier contact openings formed over stepped surfaces of the first alternating stack may extend through the first alternating stack, or may stop on the stepped surfaces. Sacrificial first-tier opening fill portions are formed in the first-tier openings, and a second-tier structure can be formed over the first-tier structure. Memory openings including volumes of the first-tier memory openings are formed through the multi-tier structure, and memory stack structures are formed in the memory openings. Various contact openings are formed through the multi-tier structure, and various contact via structures are formed in the contact openings.

公开(公告)号：US10388666B1

公开(公告)日：2019-08-20

申请号：US16020739

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Zhixin Cui ,  Murshed Chowdhury ,  Johann Alsmeier ,  Tong Zhang

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157 ,  H01L23/522 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L27/11573

Abstract: A first-tier structure including a first alternating stack of first insulating layers and first spacer material layers is formed over a substrate. First-tier memory openings and at least one type of first-tier contact openings can be formed simultaneously employing a same anisotropic etch process. The first-tier contact openings formed over stepped surfaces of the first alternating stack may extend through the first alternating stack, or may stop on the stepped surfaces. Sacrificial first-tier opening fill portions are formed in the first-tier openings, and a second-tier structure can be formed over the first-tier structure. Memory openings including volumes of the first-tier memory openings are formed through the multi-tier structure, and memory stack structures are formed in the memory openings. Various contact openings are formed through the multi-tier structure, and various contact via structures are formed in the contact openings.

公开(公告)号：US10224407B2

公开(公告)日：2019-03-05

申请号：US15444725

申请日：2017-02-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Murshed Chowdhury ,  Andrew Lin ,  James Kai ,  Yanli Zhang ,  Johann Alsmeier

IPC: H01L21/28 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

Abstract: A trench having a uniform depth is provided in an upper portion of a semiconductor substrate. A continuous dielectric material layer is formed, which includes a gate dielectric that fills an entire volume of the trench. A gate electrode is formed over the gate dielectric such that the gate electrode overlies a center portion of the gate dielectric and does not overlie a first peripheral portion and a second peripheral portion of the gate dielectric that are located on opposing sides of the center portion of the gate dielectric. After formation of a dielectric gate spacer, a source extension region and a drain extension region are formed within the semiconductor substrate by doping respective portions of the semiconductor substrate.

公开(公告)号：US20180240527A1

公开(公告)日：2018-08-23

申请号：US15923064

申请日：2018-03-16

Applicant: SanDisk Technologies LLC

Inventor： Zhengyi Zhang ,  Yingda Dong ,  James Kai ,  Johann Alsmeier

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/28

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/28 ,  G11C16/3459

Abstract: A three-dimensional stacked memory device is configured to provide uniform programming speeds of different sets of memory strings formed in memory holes. In a process for removing sacrificial material from word line layers, a block oxide layer in the memory holes is etched away relatively more when the memory hole is relatively closer to an edge of the word line layers where an etchant is introduced. A thinner block oxide layer is associated with a faster programming speed. To compensate, memory strings at the edges of the word line layers are programmed together, separate from the programming of interior memory strings. A program operation can use a higher initial program voltage for programming the interior memory strings compared to the edge memory strings.

公开(公告)号：US20180211970A1

公开(公告)日：2018-07-26

申请号：US15927688

申请日：2018-03-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Murshed Chowdhury ,  Jin Liu ,  Johann Alsmeier

IPC: H01L27/11582 ,  H01L29/51 ,  H01L21/02 ,  H01L29/423 ,  H01L29/417 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11519 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02192 ,  H01L21/02494 ,  H01L21/02587 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/41741 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/518

Abstract: A three-dimensional memory device including self-aligned drain select level electrodes is provided. Memory stack structures extend through an alternating stack of insulating layers and spacer material layers. Each of the memory stack structures includes a memory film and a memory level channel portion. Drain select level channel portions are formed over the memory level channel portions with respective lateral shifts with respect to underlying memory stack structures. The direction of lateral shifts alternates from row to row for each row of drain select level channel portions. Drain select level gate dielectrics and drain select level gate electrodes are formed on the drain select level channel portions. Each drain select level gate electrode controls two rows of drain select level channel portions, and is laterally spaced from neighboring drain select level gate electrodes.

公开(公告)号：US10020363B2

公开(公告)日：2018-07-10

申请号：US15458269

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki Ogawa ,  Yasuo Kasagi ,  Satoshi Shimizu ,  Kazuyo Matsumoto ,  Yohei Masamori ,  Jixin Yu ,  Tong Zhang ,  James Kai

IPC: H01L29/10 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

CPC classification number: H01L29/1037 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: Sacrificial semiconductor material portions are connected by a sacrificial semiconductor line extending along a different horizontal direction and protruding into an underlying source conductive layer. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through the sacrificial semiconductor material portions. A backside trench can be formed through the vertically alternating stack employing the sacrificial semiconductor line as an etch stop structure. Source strap material portions providing lateral electrical contact to semiconductor channels of the memory stack structures can be formed by replacement of sacrificial semiconductor material portions and the sacrificial semiconductor line with source strap material portions. Structural-reinforcement portions may be employed to provide structural stability during the replacement process.

公开(公告)号：US09922987B1

公开(公告)日：2018-03-20

申请号：US15468732

申请日：2017-03-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yuki Mizutani ,  James Kai ,  Fumiaki Toyama ,  Shigehiro Fujino ,  Johann Alsmeier

IPC: H01L27/115 ,  H01L27/11548 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L23/485

CPC classification number: H01L27/11548 ,  H01L23/485 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: Memory stack structures can be formed through an alternating stack of insulating layers and spacer material layers that are formed as, or are subsequently replaced with, electrically conductive layers. The memory stack structures can be formed as rows having a first pitch. Additional insulating layers and at least one drain select level dielectric layer are formed over the alternating stack. Drain select level openings are formed in rows having a smaller second pitch. Partial replacement of the at least one drain select level dielectric layer forms spaced apart electrically conductive line structures that surround a respective plurality of drain select level openings. Drain select level channel portions are subsequently formed in respective drain select level openings.

公开(公告)号：US09831266B2

公开(公告)日：2017-11-28

申请号：US15225492

申请日：2016-08-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Johann Alsmeier ,  Jin Liu ,  Yanli Zhang

IPC: H01L27/115 ,  H01L23/535 ,  H01L27/11582 ,  H01L27/1157 ,  H01L21/306 ,  H01L21/768 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/30604 ,  H01L21/76895 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/42344

Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. An alternating sequence of support pedestal structures and conductive rail structures extending along a same horizontal direction are provided between the substrate and the alternating stack. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support pedestal structure. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure, and is electrically isolated from an adjacent support pedestal structure by a portion of a memory film. The conductive rail structures can function as source regions of memory device.

公开(公告)号：US11552094B2

公开(公告)日：2023-01-10

申请号：US17031080

申请日：2020-09-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Murshed Chowdhury ,  Masaaki Higashitani ,  Johann Alsmeier

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and an array of memory opening fill structures extending through the alternating stack, an array of drain-select-level assemblies overlying the alternating stack and having a same two-dimensional periodicity as the array of memory opening fill structures, a first strip electrode portion laterally surrounding a first set of multiple rows of drain-select-level assemblies within the array of drain-select-level assemblies, and a drain-select-level isolation strip including an isolation dielectric that contacts the first strip electrode portion and laterally spaced from the drain-select-level assemblies and extending between the first strip electrode portion and a second strip electrode portion.