公开(公告)号：US11705203B2

公开(公告)日：2023-07-18

申请号：US17352095

申请日：2021-06-18

Applicant: SanDisk Technologies LLC

Inventor： Henry Chin ,  Hua-Ling Cynthia Hsu ,  Wei Zhao ,  Fanglin Zhang

IPC: G11C16/00 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  G06F1/20 ,  G11C16/04 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27

CPC classification number: G11C16/14 ,  G06F1/20 ,  G11C16/26 ,  G11C16/3459 ,  G11C16/0483 ,  H01L25/0657 ,  H01L2225/06562 ,  H10B43/10 ,  H10B43/27

Abstract: Techniques disclosed herein cope with temperature effects in non-volatile memory systems. A control circuit is configured to sense a current temperature of the memory system and read, verify, program, and erase data in non-volatile memory cells by modifying one or more read/verify/program/erase parameters based on a temperature compensation value. The control circuit is further configured to read, verify, program, and erase data by accessing a historical temperature value stored in the memory system, the historical temperature value comprising a temperature at which a previous read, verify, program or erase occurred and measuring a current temperature value. The control circuit determines the temperature compensation value by applying a smoothing function. The smoothing function determines the temperature compensation value by selecting either the historical temperature value or the current temperature value as the temperature compensation value based on a difference between the historical temperature value and the current temperature relative to a threshold, or calculating the temperature compensation value, different from the current temperature value or the historical temperature value, based a smoothing function which utilizes the current temperature value and the historical temperature value.

公开(公告)号：US11101288B2

公开(公告)日：2021-08-24

申请号：US16710572

申请日：2019-12-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli Zhang ,  Dong-il Moon ,  Raghuveer S. Makala ,  Peng Zhang ,  Wei Zhao ,  Ashish Baraskar

IPC: H01L27/11582 ,  H01L21/28 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11556

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a memory film and a vertical semiconductor channel. At least one of the electrically conductive layers contains a first conductive material portion having a respective inner sidewall that contacts a respective one of the memory films at a vertical interface, and a second conductive material portion that has a different composition from the first conductive material portion, and contacting the first electrically conductive material portion. The first conductive material portion has a lower work function than the second conductive material portion.

公开(公告)号：US10957394B1

公开(公告)日：2021-03-23

申请号：US16785973

申请日：2020-02-10

Applicant: SanDisk Technologies LLC

Inventor： Han-Ping Chen ,  Wei Zhao ,  Henry Chin

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11582 ,  H01L27/1157 ,  G11C16/34

Abstract: Apparatuses and techniques are described for pre-charging NAND string channels in a pre-charge phase of a program operation. In one aspect, a hole-type pre-charge process is used at the source end of a NAND string, where a bottom of the NAND string is connected to a p-well of a substrate. By applying a positive voltage to the p-well and a lower voltage, such as 0 V or a negative voltage, to the source-side select gate transistors and the memory cells, the holes from the p-well are injected into the channel In another approach, the hole-type pre-charge process and an electron-type pre-charge process are used sequentially in separate time periods. In another approach, the hole-type pre-charge process is used at the source end of a NAND string while the electron-type pre-charge process is used at the drain end of the NAND string.

公开(公告)号：US10685978B1

公开(公告)日：2020-06-16

申请号：US16267592

申请日：2019-02-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ching-Huang Lu ,  Wei Zhao ,  Yanli Zhang ,  James Kai

IPC: H01L29/792 ,  H01L21/00 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526

Abstract: Electrical isolation between adjacent stripes of drain-select-level electrically conductive layers can be provided by forming a drain-select-level isolation structure between neighboring rows of memory stack structures. The drain-select-level isolation structure can partially cut through upper regions of the neighboring rows of memory stack structures. Vertical semiconductor channels of the neighboring rows of memory stack structures include a lower tubular segment and an upper semi-tubular segment that contact the drain-select-level isolation structure. Electrical current through drain select levels is limited to the semi-tubular segment of each vertical semiconductor channel. Alternatively, the drain-select-level isolation structure can be formed around the memory stack structures within the neighboring rows of memory stack structures. Ion implantation can be used to suppress conduction of electrical current through portions of vertical semiconductor channels that are proximal to the drain-select-level isolation structure.

公开(公告)号：US10685723B1

公开(公告)日：2020-06-16

申请号：US16227668

申请日：2018-12-20

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Wei Zhao ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/04 ,  G11C11/56 ,  G11C16/32 ,  G11C16/26 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556

Abstract: Techniques for reducing read disturb of memory cells in a two-tier stack having a lower tier and an upper tier separated by an interface. In a read operation, the channels of NAND strings are discharged before reading the selected memory cells. A discharge period is set based on a position of the selected word line in a stack or block of memory cells. The discharge period is longer when the selected word line is in the lower tier than in the upper tier. Additionally, the discharge period is longer when the selected word line is at a top of the lower tier than at a bottom of the lower tier. Other options to increase the discharge include increasing a ramp up rate and a peak level of the word line voltages during the discharge period as a function of the position of the selected word line.

公开(公告)号：US09640273B1

公开(公告)日：2017-05-02

申请号：US15247746

申请日：2016-08-25

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Yingda Dong ,  Wei Zhao

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G11C16/14 ,  G11C16/08

CPC classification number: G11C16/3431 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427

Abstract: Techniques are provided for preventing program disturb when programming a memory device. Hot electron injection program disturb is prevented or reduced. Voltage boosting of the NAND channel of a program inhibited NAND string may be controlled in a manner to reduce or eliminate a lateral electric field that could possibly accelerate electrons in the NAND channel. If the electrons gain enough energy due to the lateral electric field, they could potentially be injected into the charge storage region of a memory cell, thereby causing program disturb. Thus, the voltage boosting can prevent or reduce injection of hot electrons from the NAND channel to a charge storage region of a NAND memory cell during a programming operation, thereby preventing or reducing program disturb.

公开(公告)号：US11894051B2

公开(公告)日：2024-02-06

申请号：US17752524

申请日：2022-05-24

Applicant: SanDisk Technologies LLC

Inventor： Dong-Il Moon ,  Abhijith Prakash ,  Wei Zhao ,  Henry Chin

IPC: G11C7/00 ,  G11C11/56 ,  G11C16/26

CPC classification number: G11C11/5642 ,  G11C11/5671 ,  G11C16/26

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the strings and is configured to apply a read voltage to a selected ones of the plurality of word lines during a read operation and ramp down to a discharge voltage at an end of the read operation and apply a ready voltage to the selected ones of the plurality of word lines during a ready period of time following the read operation. The control means is also configured to adjust at least one of the discharge voltage and the ready voltage based on a temperature of the memory apparatus.

公开(公告)号：US10811110B1

公开(公告)日：2020-10-20

申请号：US16903294

申请日：2020-06-16

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Wei Zhao ,  Henry Chin

IPC: G11C16/34 ,  G11C16/24 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

Abstract: Techniques are described for reducing an injection type of program disturb in a memory device during the pre-charge phase of a program loop. In one approach, a pre-charge voltage on the selected word line and drain side word lines is adjusted based on a risk of the injection type of program disturb. Risk factors such as temperature, WLn position, Vpgm and the selected sub-block, can be used to set the pre-charge voltage to be lower when the risk is higher. In another approach, the pre-charge voltage on the source side word lines is adjusted to reduce a channel gradient and/or the amount of time in which the injection type of program disturb occurs.

公开(公告)号：US10790003B1

公开(公告)日：2020-09-29

申请号：US16528349

申请日：2019-07-31

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Wei Zhao

IPC: G11C11/22 ,  G11C11/406

Abstract: Techniques are described for maintaining a pre-charge voltage in a NAND string in a program operation. After a pre-charge voltage is applied to the channel of a NAND string, the word line voltages are controlled to avoid a large channel gradient which generates electron-hole pairs, where the electrons can pull down the channel boosting level on the drain side of the selected word line. In one approach, the word line voltages of a group of one or more source side word lines adjacent to the selected word line are increased directly from the level used during pre-charge to a pass voltage. The word line voltages of other source side word lines, and of drain side word lines, can be decreased and then increased to the pass voltage to provide a large voltage swing which couples up the channel.

公开(公告)号：US10593411B1

公开(公告)日：2020-03-17

申请号：US16281572

申请日：2019-02-21

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Wei Zhao

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24 ,  G11C16/28 ,  G11C7/10 ,  G11C11/56 ,  G11C7/04 ,  G11C16/32

Abstract: Techniques are described for reducing an injection type of program disturb in a memory device. A charge isolation region is created in a channel of a NAND string on the source side of the selected word line, WLn, and spaced apart from WLn by one or more other word lines, when the program voltage is increased to a program voltage (Vpgm). The isolation region is created by applying 0 V or other low voltage to an isolation word line. The isolation region is maintained for a first portion of a time period in which Vpgm is applied. The charge isolation region can be modified based on factors associated with a risk of program disturb including the magnitude of Vpgm, the position of WLn in a set of word lines and an ambient temperature.