公开(公告)号：US20240250182A1

公开(公告)日：2024-07-25

申请号：US18624513

申请日：2024-04-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya ONUKI ,  Kiyoshi KATO ,  Tomoaki ATSUMI ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H10B12/00

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42384 ,  H01L29/78696 ,  H10B12/31

Abstract: A novel memory device is provided. The memory device includes a plurality of first wirings extending in a first direction, a plurality of memory element groups, and an oxide layer extending along a side surface of the first wiring. Each of the memory element groups includes a plurality of memory elements. Each of the memory elements includes a first transistor and a capacitor. A gate electrode of the first transistor is electrically connected to the first wiring. The oxide layer includes a region in contact with a semiconductor layer of the first transistor. A second transistor is provided between the adjacent memory element groups. A high power supply potential is supplied to one or both of a source electrode and a drain electrode of the second transistor.

公开(公告)号：US20240138169A1

公开(公告)日：2024-04-25

申请号：US18546685

申请日：2022-02-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Koji KUSUNOKI ,  Kazunori WATANABE ,  Tomoaki ATSUMI ,  Satoshi YOSHIMOTO

IPC: H10K39/34 ,  G06F3/042 ,  G06V40/13 ,  G09G3/3233 ,  H10K59/131

CPC classification number: H10K39/34 ,  G06F3/042 ,  G06V40/1318 ,  G09G3/3233 ,  H10K59/131 ,  G06F2203/04108 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2354/00 ,  G09G2360/14

Abstract: A semiconductor device having a light sensing function and including a high-resolution display portion is provided. The semiconductor device includes a plurality of pixels, and the pixels each include first and second light-receiving devices, first to fifth transistors, a capacitor, and a first wiring. One electrode of the first light-receiving device is electrically connected to the first wiring, and the other electrode is electrically connected to one of a source and a drain of the first transistor. One electrode of the second light-receiving device is electrically connected to the first wiring, and the other electrode is electrically connected to one of a source and a drain of the second transistor. The other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor. The other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor, one of a source and a drain of the third transistor, and a gate of the fourth transistor.

公开(公告)号：US20230127474A1

公开(公告)日：2023-04-27

申请号：US17892190

申请日：2022-08-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hitoshi KUNITAKE ,  Ryunosuke HONDA ,  Tomoaki ATSUMI

IPC: H10B12/00 ,  G11C11/405 ,  G11C11/4074 ,  H01L29/66

Abstract: A semiconductor device capable of obtaining the threshold voltage of a transistor is provided. The semiconductor device includes a first transistor, a first capacitor, a first output terminal, a first switch, and a second switch. A gate and a source of the first transistor are electrically connected to each other. A first terminal of the first capacitor is electrically connected to the source. A second terminal and the first output terminal of the first capacitor are electrically connected to a back gate of the first transistor. The first switch controls input of a first voltage to the back gate. A second voltage is input to a drain of the first transistor. The second switch controls input of a third voltage to the source.

公开(公告)号：US20220085019A1

公开(公告)日：2022-03-17

申请号：US17419745

申请日：2020-02-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi KUNITAKE ,  Tatsuya ONUKI ,  Tomoaki ATSUMI ,  Kiyoshi KATO

IPC: H01L27/108 ,  H01L21/8239 ,  H01L29/786 ,  G11C29/52

Abstract: A memory device having an error detection function and being capable of storing a large amount of data per unit area is provided. A driver circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers each of which includes a memory cell using the thin film transistor can be stacked over the semiconductor substrate, so that the amount of data that can be stored per unit area can be increased. Part of a peripheral circuit including the memory device can be formed using a thin film transistor, and thus, an error detection circuit is formed using the thin film transistor and stacked over the semiconductor substrate.

公开(公告)号：US20210398988A1

公开(公告)日：2021-12-23

申请号：US17466442

申请日：2021-09-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Tamae MORIWAKA ,  Yuta ENDO

IPC: H01L27/115 ,  H01L29/786 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/06 ,  G11C7/16 ,  G11C8/14 ,  G11C11/403 ,  G11C11/408 ,  G11C11/24 ,  H01L29/24

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j-lth sub memory cell.

公开(公告)号：US20190157309A1

公开(公告)日：2019-05-23

申请号：US16256348

申请日：2019-01-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshinori IEDA ,  Atsuo ISOBE ,  Yutaka SHIONOIRI ,  Tomoaki ATSUMI

IPC: H01L27/12 ,  H01L29/786 ,  H01L27/105 ,  H01L29/78 ,  H01L29/04 ,  H01L29/16 ,  H01L29/49 ,  H01L29/423 ,  H01L29/24 ,  H01L27/108 ,  H01L49/02 ,  H01L27/092 ,  H01L27/115

Abstract: Provided is a semiconductor device which has low power consumption and can operate at high speed. The semiconductor device includes a memory element including a first transistor including crystalline silicon in a channel formation region, a capacitor for storing data of the memory element, and a second transistor which is a switching element for controlling supply, storage, and release of charge in the capacitor. The second transistor is provided over an insulating film covering the first transistor. The first and second transistors have a source electrode or a drain electrode in common.

公开(公告)号：US20180109267A1

公开(公告)日：2018-04-19

申请号：US15832114

申请日：2017-12-05

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yutaka SHIONOIRI ,  Kiyoshi KATO ,  Tomoaki ATSUMI

IPC: H03M1/00 ,  H03M1/12 ,  G11C27/02 ,  H03M1/46

CPC classification number: H03M1/002 ,  G11C27/02 ,  H03M1/1245 ,  H03M1/466

Abstract: An object is to reduce power consumption of an analog-digital converter circuit. An analog potential obtained in a sensor or the like is held in a sample-and-hold circuit including a transistor with an extremely low off-state current. In the sample-and-hold circuit, the analog potential is held in a node which is able to hold a charge by turning off the transistor. Then, power supply to a buffer circuit or the like included in the sample-and-hold circuit is stopped to reduce power consumption. In a structure where a potential is hold in each node, power consumption can be further reduced when a transistor with an extremely low off-state current is connected to a node holding a potential of a comparator, a successive approximation register, a digital-analog converter circuit, or the like, and power supply to these circuits is stopped.

公开(公告)号：US20170179132A1

公开(公告)日：2017-06-22

申请号：US15447672

申请日：2017-03-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshinori IEDA ,  Atsuo ISOBE ,  Yutaka SHIONOIRI ,  Tomoaki ATSUMI

IPC: H01L27/105 ,  H01L29/24 ,  H01L27/108 ,  H01L29/786 ,  H01L27/12 ,  H01L49/02

CPC classification number: H01L27/1207 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10805 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L28/40 ,  H01L29/04 ,  H01L29/16 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78 ,  H01L29/78648 ,  H01L29/7869

Abstract: Provided is a semiconductor device which has low power consumption and can operate at high speed. The semiconductor device includes a memory element including a first transistor including crystalline silicon in a channel formation region, a capacitor for storing data of the memory element, and a second transistor which is a switching element for controlling supply, storage, and release of charge in the capacitor. The second transistor is provided over an insulating film covering the first transistor. The first and second transistors have a source electrode or a drain electrode in common.

公开(公告)号：US20150363136A1

公开(公告)日：2015-12-17

申请号：US14731940

申请日：2015-06-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru UESUGI ,  Tomoaki ATSUMI ,  Naoaki TSUTSUI ,  Hikaru TAMURA ,  Takahiko ISHIZU ,  Takuro OHMARU

IPC: G06F3/06 ,  G06F11/14

CPC classification number: G06F12/00 ,  G11C5/00 ,  H01L27/0688 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7782

Abstract: A semiconductor device including a register controller and a processor which includes a register is provided. The register includes a first circuit and a second circuit which includes a plurality of memory portions. The first circuit and the plurality of memory portions can store data by an arithmetic process of the processor. Which of the plurality of memory portions the data is stored in depends on a routine by which the data is processed. The register controller switches the routine in response to an interrupt signal. The register controller can make any one of the plurality of memory portions which corresponds to the routine store the data in the first circuit every time the routine is switched. The register controller can make data stored in any one of the plurality of memory portions which corresponds to the routine be stored in the first circuit every time the routine is switched.

Abstract translation: 提供一种包括寄存器控制器和包括寄存器的处理器的半导体器件。 寄存器包括第一电路和包括多个存储器部分的第二电路。 第一电路和多个存储器部分可以通过处理器的算术处理来存储数据。 存储数据的多个存储器部分中的哪一个取决于数据被处理的程序。 寄存器控制器响应中断信号切换程序。 寄存器控制器可以使每次该例程的多个存储器部分中的任何一个存储在第一电路中。 寄存器控制器可以在每次该例程被切换时使存储在与该程序相对应的多个存储器部分中的任何一个存储器中的数据存储在第一电路中。

公开(公告)号：US20150263047A1

公开(公告)日：2015-09-17

申请号：US14637557

申请日：2015-03-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime KIMURA ,  Tomoaki ATSUMI ,  Shunpei YAMAZAKI

IPC: H01L27/12 ,  G11C11/24 ,  H01L29/786

CPC classification number: H01L27/1222 ,  G11C11/24 ,  G11C11/56 ,  G11C11/565 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/53 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/1225 ,  H01L29/7869

Abstract: A semiconductor device that can store multilevel data is provided. A circuit includes a transistor. The circuit includes another circuit including a terminal, for example. The terminal is connected to a gate of the transistor. One of a source and a drain of the transistor is connected to a wiring, and the other of the source and the drain is connected to another wiring.

Abstract translation: 提供了可以存储多级数据的半导体器件。 电路包括晶体管。 该电路包括例如包括端子的另一电路。 端子连接到晶体管的栅极。 晶体管的源极和漏极之一连接到布线，源极和漏极中的另一个连接到另一布线。