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公开(公告)号：US11908947B2
公开(公告)日：2024-02-20
申请号：US17628091
申请日：2020-07-27
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Munehiro Kozuma , Takahiko Ishizu , Takeshi Aoki , Masashi Fujita , Kazuma Furutani , Kousuke Sasaki
CPC classification number: H01L29/7869 , G06F7/5443 , G11C7/1069 , G11C7/1096 , G11C7/12 , G11C7/14 , H10B12/50 , H01L27/1225
Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a CPU and an accelerator. The accelerator includes a first memory circuit and an arithmetic circuit. The first memory circuit includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The arithmetic circuit includes a second transistor. The second transistor includes a semiconductor layer containing silicon in a channel formation region. The first transistor and the second transistor are provided to be stacked. The CPU includes a CPU core including a flip-flop provided with a backup circuit. The backup circuit includes a third transistor. The third transistor includes a semiconductor layer containing a metal oxide in a channel formation region.
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公开(公告)号：US11799430B2
公开(公告)日：2023-10-24
申请号：US17635268
申请日：2020-08-11
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Kei Takahashi , Takeshi Aoki , Munehiro Kozuma , Takayuki Ikeda
CPC classification number: H03F3/45179 , H01L27/1207 , H03K5/2472 , H01L27/1211 , H02J7/0029
Abstract: A novel comparison circuit, a novel amplifier circuit, a novel battery control circuit, a novel battery protection circuit, a power storage device, a semiconductor device, an electric device, and the like are provided. In a semiconductor device, one of a source and a drain of a first transistor is electrically connected to one of a source and a drain of a second transistor and one of a source and a drain of a third transistor; the other of the source and the drain of the third transistor is electrically connected to a first output terminal; and the other of the source and the drain of the second transistor is electrically connected to a second output terminal. The semiconductor device has a function of outputting a comparison result of a signal supplied to a gate of the second transistor and a signal supplied to a gate of the third transistor, from the first output terminal and the second output terminal; and a function of changing the potential output from the first output terminal in accordance with the potential applied to a back gate of the first transistor.
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公开(公告)号：US11330213B2
公开(公告)日：2022-05-10
申请号：US16715852
申请日：2019-12-16
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Takashi Nakagawa , Munehiro Kozuma , Yoshiyuki Kurokawa , Takayuki Ikeda
IPC: H04N5/369 , H04N5/374 , H04N5/3745 , H04N5/378 , H04N5/232 , H04N5/32 , H04N5/376 , H01L27/146 , H01L27/12 , H04N5/343 , G08B13/196
Abstract: An imaging device with low power consumption is provided. It includes a pixel capable of outputting difference data between two different frames, a circuit determining the significance of the difference data, a circuit controlling power supply, an A/D converter, and the like; obtains image data and then obtains difference data; and shuts off power supply to the A/D converter and the like in the case where it is determined that there is no difference, and continues or restarts the power supply to the A/D converter and the like when it is determined that there is a difference. Determining the significance of the difference data can be performed row by row in a pixel array or at nearly the same time in all the pixels included in the pixel array.
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公开(公告)号：US10535691B2
公开(公告)日：2020-01-14
申请号：US15177460
申请日：2016-06-09
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Yoshiyuki Kurokawa , Takayuki Ikeda , Hikaru Tamura , Munehiro Kozuma , Masataka Ikeda , Takeshi Aoki
IPC: H01L27/146 , H04N5/378 , H04N5/374 , H01L29/786 , H01L31/105 , H04N5/361
Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
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公开(公告)号：US10390075B2
公开(公告)日：2019-08-20
申请号：US15729191
申请日：2017-10-10
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Munehiro Kozuma
Abstract: A semiconductor device that is suitable for high-speed operation is provided. The semiconductor device includes a decoder. The decoder includes a first circuit. The first circuit is configured to operate in synchronization with a clock signal. The first circuit is configured to perform image processing. A circuit configuration of the first circuit can be changed. Clock gating is performed on the first circuit to prevent the clock signal from being input to the first circuit when the circuit configuration of the first circuit is being changed. A broadcasting system including the semiconductor device is also provided.
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Patent Agency Ranking
26.发明授权公开(公告)号：US09397637B2
公开(公告)日：2016-07-19
申请号：US14635117
申请日：2015-03-02
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Munehiro Kozuma , Yoshiyuki Kurokawa , Takayuki Ikeda
CPC classification number: H03K3/012 , H01L27/1207 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L29/24 , H01L29/7869 , H03B1/02 , H03K3/0315 , H03L7/0995 , H03L7/14 , H03L2207/08
Abstract: A low-power voltage controlled oscillator is provided. The voltage controlled oscillator includes (2n+1) first circuit components (n is an integer of one or more). An output terminal of the first circuit component in a k-th stage (k is an integer of one or more and 2n or less) is connected to an input terminal of the first circuit component in a (k+1)-th stage. An output terminal of the first circuit component in a (2n+1)-th stage is connected to an input terminal of the first circuit component in a first stage. One of the first circuit components includes a second circuit component and a third circuit component whose input terminal is connected to an output terminal of the second circuit component. The third circuit component includes a first transistor and a second transistor whose source-drain resistance is controlled in accordance with a signal input to a gate through the first transistor.
Abstract translation: 提供了一个低功耗压控振荡器。 压控振荡器包括（2n + 1）个第一电路部件（n为1以上的整数）。 第k级的第一电路部件的输出端子（k为1以上且2n以下的整数）在第（k + 1）级连接到第一电路部件的输入端子。 第（2n + 1）级中的第一电路部件的输出端在第一级连接到第一电路部件的输入端。 第一电路部件中的一个包括第二电路部件和第三电路部件，其输入端子连接到第二电路部件的输出端子。 第三电路部件包括第一晶体管和第二晶体管，源极 - 漏极电阻根据通过第一晶体管输入到栅极的信号来控制。
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27.发明授权Semiconductor device applicable to a multi-context programmable logic device 有权适用于多上下文可编程逻辑器件的半导体器件公开(公告)号：US09384813B2
公开(公告)日：2016-07-05
申请号：US14613554
申请日：2015-02-04
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Takeshi Aoki , Munehiro Kozuma
IPC: G11C11/34 , G06F17/50 , H03K19/177
CPC classification number: G11C11/34 , G06F17/5045 , G06F17/5054 , H03K19/177 , H03K19/1776
Abstract: A low-power semiconductor device is provided. A memory device applicable to a multi-context programmable logic device (PLD) includes at least memory cells the number of which is the same as the number of contexts. Output nodes of the memory cells are electrically connected to an output node of a configuration memory through different path transistors. A circuit including a transistor and a capacitor makes a gate potential of the path transistor higher than a high-level potential. This prevents a decrease in the potential of the output node of the configuration memory due to the threshold voltage of the path transistor without an increase in power consumption.
Abstract translation: 提供了一种低功率半导体器件。 适用于多上下文可编程逻辑器件（PLD）的存储器件至少包括其数量与上下文数量相同的存储器单元。 存储单元的输出节点通过不同的路径晶体管电连接到配置存储器的输出节点。 包括晶体管和电容器的电路使路径晶体管的栅极电位高于高电位电位。 这防止由于路径晶体管的阈值电压而导致的配置存储器的输出节点的电位降低，而不增加功耗。
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公开(公告)号：US09349454B2
公开(公告)日：2016-05-24
申请号：US14636792
申请日：2015-03-03
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Takayuki Ikeda , Yoshiyuki Kurokawa , Munehiro Kozuma
CPC classification number: G11C11/24 , G11C7/16 , G11C11/40 , G11C11/404 , G11C11/405 , G11C11/4091 , G11C16/0441 , G11C16/10 , G11C27/005 , G11C27/02 , G11C27/024 , H01L21/02565 , H01L21/0262 , H01L23/528 , H01L27/1052 , H01L27/1156 , H01L27/1207 , H01L27/1225 , H01L27/1255 , H01L29/66969 , H01L29/7869 , H01L29/78693
Abstract: A semiconductor device capable of generating a signal (e.g., a potential signal or a current signal) suitable for usage environment or a purpose. The semiconductor device includes a first memory circuit, a first circuit, and a second memory circuit. The first circuit converts a digital signal input from the first memory circuit into an analog signal. The first memory circuit includes an input node, an output node, a transistor, and a capacitor. The capacitor is electrically connected to the output node. The transistor can control a conduction state between the input node and the output node. An analog signal is input to the input node from the first circuit. The transistor includes an oxide semiconductor layer where a channel formation region is formed.
Abstract translation: 能够产生适合于使用环境或目的的信号（例如，电位信号或电流信号）的半导体器件。 半导体器件包括第一存储器电路，第一电路和第二存储器电路。 第一电路将从第一存储器电路输入的数字信号转换为模拟信号。 第一存储器电路包括输入节点，输出节点，晶体管和电容器。 电容器电连接到输出节点。 晶体管可以控制输入节点和输出节点之间的导通状态。 模拟信号从第一电路输入到输入节点。 晶体管包括其中形成沟道形成区的氧化物半导体层。
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29.发明授权Photodetector including difference data generation circuit and data input selection circuit 有权光电检测器包括差分数据生成电路和数据输入选择电路公开(公告)号：US09055245B2
公开(公告)日：2015-06-09
申请号：US13623912
申请日：2012-09-21
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Munehiro Kozuma
Abstract: Adverse effects of noise are reduced. A photodetector circuit, a difference data generation circuit, and a data input selection circuit are included. The photodetector circuit has a function of generating an optical data signal. A first data signal and a second data signal is input to the difference data generation circuit and the difference data generation circuit has a function of generating difference data of data of the first data signal and data of the second data signal. The data input selection circuit has a function of determining that the data of optical data signal is regarded as data of the first data signal or data of the second data signal.
Abstract translation: 噪音的不利影响降低。 包括光电检测器电路，差分数据生成电路和数据输入选择电路。 光检测器电路具有产生光数据信号的功能。 第一数据信号和第二数据信号被输入到差数据生成电路，差数据生成电路具有产生第一数据信号的数据和第二数据信号的数据的差分数据的功能。 数据输入选择电路具有确定光数据信号的数据被认为是第一数据信号的数据或第二数据信号的数据的功能。
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公开(公告)号：US20150145559A1
公开(公告)日：2015-05-28
申请号：US14542874
申请日：2014-11-17
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Munehiro Kozuma
IPC: H03K19/177 , H01L27/12 , H01L29/786
CPC classification number: H03K19/1776 , G11C7/20 , G11C2029/4402 , H01L27/0688 , H01L27/092 , H01L27/1156 , H01L27/1225 , H01L29/785 , H01L29/7869
Abstract: To provide a highly reliable and low-power-consumption semiconductor device functioning as a programmable logic device. A monitor circuit is provided to monitor a change in the potential of a configuration memory in which a transistor is turned off to hold charge and a potential corresponding to the charge is stored as configuration data. The reset of the configuration data is controlled in accordance with the potential change. With such a structure, the configuration memory can be reconfigured before the configuration data is lost, resulting in improved reliability of the semiconductor device. In addition, reconfiguration can be performed every time data is lost. Accordingly, power consumption can be reduced as compared with the structure where reconfiguration is performed periodically.
Abstract translation: 提供用作可编程逻辑器件的高可靠性和低功耗半导体器件。 提供监视器电路以监视其中晶体管被截止以保持电荷的配置存储器的电位变化，并且与电荷相对应的电位被存储为配置数据。 根据电位变化来控制配置数据的复位。 通过这样的结构，可以在配置数据丢失之前重新配置配置存储器，从而提高半导体器件的可靠性。 此外，每当数据丢失时，都可以进行重新配置。 因此，与周期性地进行重新配置的结构相比，能够降低功耗。
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